diff options
author | Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> | 2018-10-23 02:43:05 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-25 09:26:50 +0000 |
commit | b66757fc58b9bd025148d9db690009dec487fd0d (patch) | |
tree | 419a761bf317a4c56068309e997248d9a75fe8cf /.gitignore | |
parent | ac6a5080ecb0288c980493cec8e43be2b7490aa3 (diff) |
soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions