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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-16 21:14:25 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-20 18:43:30 +0200
commitd71cfd204109b66aef0fe233e1e78e3c840fed6d (patch)
tree39ad85048b7defc516d7c8548c24166266906d1a /.gitignore
parent4b86314495b17f8d944e16cfb726cd665c7d22a1 (diff)
VIA C7 NANO: Fix early MTRR setting
It would not be possible to set MTRR for range 1MiB to 4MiB. Our RAMTOP is power of 2 and enabling cache for bottom 1MiB should cause no problems. Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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