aboutsummaryrefslogtreecommitdiff
path: root/.gitignore
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-23 07:22:59 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-30 12:30:55 +0000
commit1c105903078f85dd1be805c737b4e4da6dea0618 (patch)
treee5ea20e0c52aafe2850c6df8c310378cc2bc5e47 /.gitignore
parent3ba79b319ef5d47b0d16482a254de7c5c740e415 (diff)
arch/x86: Use a common timestamp.inc with romcc bootblocks
The same file was replicated three times for certain soc/intel bootblocks, yet there are no indications or need to do chipset-specific initialisation. There is no harm in storing the TSC values in MMX registers even when they would not be used. Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions