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authorJamie Chen <jamie.chen@intel.com>2020-01-15 11:17:21 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-18 11:20:12 +0000
commitc004857da06dd90be9a1ac34bd6efe2bc03fed6a (patch)
tree47f4043e511b22b72c1d3c7385ecb2c09f1f2737 /.gitignore
parent1d8568c91413c76ee147bf6c09ae87197f7e75d7 (diff)
soc/intel/cannonlake: Add chip config for SATA strength
Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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0 files changed, 0 insertions, 0 deletions