soc/amd/cezanne: save chipset state to CBMEM

Guybrush complains that this is missing during the boot, so add it to
cezanne. I verified that the registers in gpio.c are correct.

BUG=b:184549804
TEST=Build and boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

0 files changed, 0 insertions, 0 deletions