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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-03-06 16:46:39 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-09 08:08:26 +0000
commit9900cf80091ad1796c78c04b6ef6302410444480 (patch)
tree9b67ea743db43287125b5635c0d85fafa2250645 /.clang-format
parent7e303581bcda7d7a4a90d75a9b6f6698d55287ce (diff)
mb/intel/tglrvp: Add memory config for Tiger Lake UP4
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which includes 1. DQ/DQs Mapping 2. Board id Support 3. SPD indexing BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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