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authorJohn Zhao <john.zhao@intel.com>2019-05-23 16:22:21 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-05-29 20:07:26 +0000
commit64fb5aa9c3e50a49d2ecc153ff8c597e203475bc (patch)
tree8fddb316348b4277417feb5ced776ba479053ba5 /.clang-format
parent3d90d3bfce7b3e2a885bb4722ecb3a5c127e2882 (diff)
soc/intel/common: Set GSPI clock value to prevent division by zero
Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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