soc/intel/cannonlake: Reserve PMC IO resources

PMC controller gets hidden during FSP Silicon initialization
using sideband interface on CNP-PCH. Hence unable to reserve
PMC IO resources during PCI enumeration process. This causes
hang issue on non-chrome platform with CNP-PCH due to ABASE
corruption.

This patch ensures PMC IO resource (ABASE) is getting reserved
(IO address 0x1800-0x1900) and ACPI base is not overwritten by
other devices.

TEST=ABASE range is reserved along with LPC IO range during PCI
enumeration.

PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0
flags c0000100 index 20

Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions