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| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-20 20:33:10 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-03-24 14:47:45 +0100 |
| commit | 6e260fc873d38f2b836402e58c8660160b159e60 (patch) | |
| tree | bbf8e9929b2efc650296f8af97ff79278caf59ad /.checkpatch.conf | |
| parent | ccc21ca6856563f76f4da9cbfd7433e2ece3f29e (diff) | |
soc/intel/skylake: Use C entry code for MTRR programming
Make skylake cache as ram SPI mapped MTRR programming
align with apollolake code.
Change-Id: I87a5c655da8ff5f6d8ef86907b7ae2263239b1ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18923
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to '.checkpatch.conf')
0 files changed, 0 insertions, 0 deletions