summaryrefslogtreecommitdiff
path: root/.checkpatch.conf
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-05-01 18:31:48 +0200
committerPatrick Rudolph <siro@das-labor.org>2020-08-11 05:14:01 +0000
commitd0581315869331c4e934368cbb535692b486ebbc (patch)
tree5ca9b74dc9b64d22e5f1b6e4672d24c2e225956f /.checkpatch.conf
parent173493784dd07ac1cbf055a0b26c55f9bd1f5a28 (diff)
nb/intel/sandybridge/raminit: Add ECC debug code
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to '.checkpatch.conf')
0 files changed, 0 insertions, 0 deletions