soc/intel/cannonlake: Enable ISH from device

PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.

BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.

Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

0 files changed, 0 insertions, 0 deletions