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authorV Sowmya <v.sowmya@intel.com>2020-12-02 22:32:07 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-12-05 05:36:29 +0000
commit5fc798f40e994b57047512a9fa6ff9a13630cfa4 (patch)
treea652b545450f5b8b7f12464b2edf0cd852976e2d /.checkpatch.conf
parent0247fcf87b8574b8b9ecd1f49d5b7f4087384c83 (diff)
device/pci_id: Add TCSS PCI IDs for Alderlake
Add the PCI IDs for Alderlake TCSS, * USB xHCI * USB xDCI * TBT DMA * TBT PCIe Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48242 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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