mb/*/*: Remove AMD family14 boards

These boards use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I3495d140a244bbbf63e846fcd963d69907e09719
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

243 files changed, 0 insertions, 20586 deletions

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
deleted file mode 100644
index 72bd046b5b..0000000000
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*  Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS      Status;
-	MEM_DATA_STRUCT   *MemData;
-	UINT32            GpioMmioAddr;
-	UINT8             Data8;
-	UINT8             TempData8;
-
-	MemData = ConfigPtr;
-
-	Status  = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO  *ResetInfo;
-
-	UINT32  GpioMmioAddr;
-	UINT8   Data8;
-
-	ResetInfo = ConfigPtr;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
deleted file mode 100644
index 3706b3335d..0000000000
--- a/src/mainboard/amd/inagua/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_INAGUA
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_SMSC_KBC1100
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/inagua"
-
-config MAINBOARD_PART_NUMBER
-	default "Inagua"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string "VGA device PCI IDs"
-	depends on VGA_BIOS
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_AMD_INAGUA
diff --git a/src/mainboard/amd/inagua/Kconfig.name b/src/mainboard/amd/inagua/Kconfig.name
deleted file mode 100644
index 668b22a7d7..0000000000
--- a/src/mainboard/amd/inagua/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_INAGUA
-	bool "Inagua"
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c
deleted file mode 100644
index 0338115439..0000000000
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- * use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/inagua/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/inagua/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/inagua/acpi/routing.asl b/src/mainboard/amd/inagua/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/inagua/acpi/sata.asl b/src/mainboard/amd/inagua/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/inagua/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/inagua/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/inagua/acpi/superio.asl b/src/mainboard/amd/inagua/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/inagua/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/inagua/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/inagua/board_info.txt b/src/mainboard/amd/inagua/board_info.txt
deleted file mode 100644
index b351b8e696..0000000000
--- a/src/mainboard/amd/inagua/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: eval
diff --git a/src/mainboard/amd/inagua/bootblock.c b/src/mainboard/amd/inagua/bootblock.c
deleted file mode 100644
index a13136c105..0000000000
--- a/src/mainboard/amd/inagua/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/smsc/kbc1100/kbc1100.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	kbc1100_early_init(0x2e);
-	kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
deleted file mode 100644
index 73216349ce..0000000000
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/inagua/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
deleted file mode 100644
index d5a4e45415..0000000000
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
-			device pci 5.0 off end # PCIE P2P bridge MXM lane 1
-			device pci 6.0 on end # PCIE P2P bridge  LAN
-			device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on # LPC	0x439d
-				chip superio/smsc/kbc1100
-					device pnp 2e.7 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-				end # kbc1100
-			end #LPC
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on end # OHCI FS/LS USB
-			device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 on end # PCIe PortA  Express Card
-			device pci 15.1 on end # PCIe PortB  NEC USB3.0
-			device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
-			device pci 15.3 on end # PCIe PortD  PCIE X1 SLOT
-			device pci 16.0 on end # OHCI USB 10-13
-			device pci 16.2 on end # EHCI USB 10-13
-			register "gpp_configuration" = "4" #1:1:1:1
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
deleted file mode 100644
index d364649207..0000000000
--- a/src/mainboard/amd/inagua/mainboard.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00,
-	[0x18] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
-	[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
-	[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	[0x50] = 0x10, 0x11, 0x12, 0x13
-};
-
-static void init_gpios(void)
-{
-	/**
-	 * GPIO32 Pcie Device DeAssert for APU
-	 * GPIO25 Pcie LAN,       APU GPP2
-	 * GPIO02 MINIPCIE SLOT1, APU GPP3
-	 * GPIO50 Pcie Device DeAssert for Hudson Southbridge
-	 * GPIO05 Express Card,     SB  GPP0
-	 * GPIO26 NEC USB3.0GPPUSB, SB  GPP1
-	 * GPIO00 MINIPCIE SLOT2,   SB  GPP2
-	 * GPIO05 Pcie X1 Slot,     SB  GPP3
-	 */
-
-	/* Multi-function pins switch to GPIO0-35, these pins are shared with
-	 * PCI pins, make sure Hudson PCI device is disabled.
-	 */
-	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
-
-	/* select IOMux to function1/2, corresponds to GPIO */
-	iomux_write8(0x32, (iomux_read8(0x32) & 0xfc) | 1);
-	iomux_write8(0x50, (iomux_read8(0x50) & 0xfc) | 2);
-
-	/* output low */
-	gpio_100_write8(0x20, 0x48);
-	gpio_100_write8(0x32, 0x48);
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-
-	/* Inagua mainboard specific setting */
-	init_gpios();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
deleted file mode 100644
index fb978b8287..0000000000
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO	*ResetInfo;
-
-	UINT32	GpioMmioAddr;
-	UINT8	 Data8;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	switch (ResetInfo->ResetId)
-	{
-	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
-			Data8 |= BIT6;
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return	Status;
-}
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
deleted file mode 100644
index 66a05ee3c4..0000000000
--- a/src/mainboard/amd/persimmon/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_PERSIMMON
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/persimmon"
-
-config MAINBOARD_PART_NUMBER
-	default "Persimmon"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_AMD_PERSIMMON
diff --git a/src/mainboard/amd/persimmon/Kconfig.name b/src/mainboard/amd/persimmon/Kconfig.name
deleted file mode 100644
index ba24b13aa4..0000000000
--- a/src/mainboard/amd/persimmon/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_PERSIMMON
-	bool "Persimmon"
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c
deleted file mode 100644
index 14fff7da30..0000000000
--- a/src/mainboard/amd/persimmon/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/persimmon/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/persimmon/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/persimmon/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
deleted file mode 100644
index b7fd53af8c..0000000000
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },	/* Dev 12, INTA, handled by INTC device, Global */
-		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/persimmon/acpi/sata.asl b/src/mainboard/amd/persimmon/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/persimmon/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/persimmon/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/persimmon/acpi/superio.asl b/src/mainboard/amd/persimmon/acpi/superio.asl
deleted file mode 100644
index d2d8a44c23..0000000000
--- a/src/mainboard/amd/persimmon/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/amd/persimmon/acpi/usb_oc.asl b/src/mainboard/amd/persimmon/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/persimmon/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/persimmon/board_info.txt b/src/mainboard/amd/persimmon/board_info.txt
deleted file mode 100644
index 85cb19a9d9..0000000000
--- a/src/mainboard/amd/persimmon/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/persimmon/bootblock.c b/src/mainboard/amd/persimmon/bootblock.c
deleted file mode 100644
index 8dca363116..0000000000
--- a/src/mainboard/amd/persimmon/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81865f/f81865f.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/persimmon/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
deleted file mode 100644
index 5670118ac5..0000000000
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ /dev/null
@@ -1,139 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge on-board NIC
-			device pci 5.0 off end # PCIE P2P bridge
-			device pci 6.0 on end # PCIE P2P bridge PCIe slot
-			device pci 7.0 off end # PCIE P2P bridge
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/fintek/f81865f
-					device pnp 4e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 off end			# Parallel Port
-					device pnp 4e.4 off end			# Hardware Monitor
-					device pnp 4e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 4e.6 off end			# GPIO
-					device pnp 4e.a off end			# PME
-					device pnp 4e.10 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.11 on			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-				end # f81865f
-			end #LPC
-			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 off end # OHCI FS/LS USB
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB 10-13
-			device pci 16.2 off end # EHCI USB 10-13
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-
-			#set up SB800 Fan control registers and IMC fan controls
-			register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
-			register "fan0_enabled" = "1"
-			register "fan1_enabled" = "1"
-			register "imc_fan_zone0_enabled" = "1"
-			register "imc_fan_zone1_enabled" = "1"
-
-			register "fan0_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-			register "fan1_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
-			register "imc_zone0_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
-			register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone0_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone0_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone0_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone0_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone0_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			register "imc_zone1_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
-			register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone1_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone1_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone1_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone1_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone1_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			# T56N has a Maximum operating temperature  of 90C
-			# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
-			# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
-			register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
-			register "imc_zone0_fanspeeds"  = "{100,  7,  5,  4,  3, 2, 0, 0 }"
-			register "imc_zone1_thresholds" = "{ 85, 80, 75, 65,  1, 0, 0, 0, 90 }"
-			register "imc_zone1_fanspeeds"  = "{100, 10,  6,  4,  3, 0, 0, 0 }"
-
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/persimmon/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/persimmon/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
deleted file mode 100644
index 0c60e4dc5a..0000000000
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <device/mmio.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/cimx/sb800/pci_devs.h>
-#include <northbridge/amd/agesa/family14/pci_devs.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- *
- * The Persimmon PCI INTA/B/C/D pins are connected to
- * FCH pins INTE/F/G/H on the schematic so these need
- * to be routed as well.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,
-	/* IDE, SATA */
-	[0x40] = 0x0B, 0x0B,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x0A, 0x0B, 0x0A, 0x0B
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
-	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,
-	/* IDE, SATA */
-	[0x40] = 0x11, 0x13,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x10, 0x11, 0x12, 0x13
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-/*
- * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isn't implemented to match
- * the IDSEL (dev 3) of the slot, the table is adjusted for the
- * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
- * off-chip devices should get mapped to PIRQH/E/F/G.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
-	{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
-	{IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
-	{OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* enable GPP CLK0 thru CLK1 */
-	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	misc_write8(0, 0xff);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
deleted file mode 100644
index 32c22bcfa1..0000000000
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x07
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-static const CODECENTRY persimmon_codec_alc269[] =
-{
-	/* NID, PinConfig */
-	{0x12, 0x411111F0},
-	{0x14, 0x99130110},
-	{0x21, 0x0121401F},
-	{0x17, 0x411111F0},
-	{0x18, 0x01A19820},
-	{0x19, 0x411111F0},
-	{0x1A, 0x0181302F},
-	{0x1B, 0x411111F0},
-	{0x1D, 0x40069E05},
-	{0x1E, 0x411111F0},
-	{0x20, 0x0001FFFF},
-	{0xff, 0xffffffff} /* end of table */
-};
-
-static const CODECTBLLIST codec_tablelist[] =
-{
-	{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
-	{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
deleted file mode 100644
index 935e36812f..0000000000
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS      Status;
-	MEM_DATA_STRUCT   *MemData;
-	UINT32            GpioMmioAddr;
-	UINT8             Data8;
-	UINT8             TempData8;
-
-	MemData = ConfigPtr;
-
-	Status = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS           Status;
-	PCIe_SLOT_RESET_INFO   *ResetInfo;
-	UINT32                 GpioMmioAddr;
-	UINT8                  Data8;
-
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
deleted file mode 100644
index 32eddb48c9..0000000000
--- a/src/mainboard/amd/south_station/Kconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_SOUTHSTATION
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/south_station"
-
-config MAINBOARD_PART_NUMBER
-	default "Southstation"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9806"
-
-endif # BOARD_AMD_SOUTHSTATION
diff --git a/src/mainboard/amd/south_station/Kconfig.name b/src/mainboard/amd/south_station/Kconfig.name
deleted file mode 100644
index 0cc745e3bc..0000000000
--- a/src/mainboard/amd/south_station/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_SOUTHSTATION
-	bool "Southstation"
diff --git a/src/mainboard/amd/south_station/Makefile.inc b/src/mainboard/amd/south_station/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/amd/south_station/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c
deleted file mode 100644
index 339469bb87..0000000000
--- a/src/mainboard/amd/south_station/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-	},
-	/* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux1, Hdp1)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/south_station/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/south_station/acpi/gpe.asl b/src/mainboard/amd/south_station/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/south_station/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/south_station/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/south_station/acpi/routing.asl b/src/mainboard/amd/south_station/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/south_station/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/south_station/acpi/sata.asl b/src/mainboard/amd/south_station/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/south_station/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/south_station/acpi/sleep.asl b/src/mainboard/amd/south_station/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/south_station/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/south_station/acpi/superio.asl b/src/mainboard/amd/south_station/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/south_station/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/south_station/acpi/usb_oc.asl b/src/mainboard/amd/south_station/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/south_station/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/south_station/board_info.txt b/src/mainboard/amd/south_station/board_info.txt
deleted file mode 100644
index 6391228476..0000000000
--- a/src/mainboard/amd/south_station/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: South Station
-Category: eval
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/south_station/bootblock.c b/src/mainboard/amd/south_station/bootblock.c
deleted file mode 100644
index 8dca363116..0000000000
--- a/src/mainboard/amd/south_station/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81865f/f81865f.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c
deleted file mode 100644
index 453102aa6a..0000000000
--- a/src/mainboard/amd/south_station/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/south_station/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb
deleted file mode 100644
index c873e4e904..0000000000
--- a/src/mainboard/amd/south_station/devicetree.cb
+++ /dev/null
@@ -1,89 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on end # PCIE P2P bridge 0x9604
-			device pci 5.0 on end # PCIE P2P bridge 0x9605
-			device pci 6.0 on end # PCIE P2P bridge 0x9606
-			device pci 7.0 on end # PCIE P2P bridge 0x9607
-			device pci 8.0 on end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # USB
-			device pci 12.1 on end # USB
-			device pci 12.2 on end # USB
-			device pci 13.0 on end # USB
-			device pci 13.1 on end # USB
-			device pci 13.2 on end # USB
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on # LPC        0x439d
-				chip superio/fintek/f81865f
-					device pnp 4e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 off end			# Parallel Port
-					device pnp 4e.4 off end			# Hardware Monitor
-					device pnp 4e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-					end
-					device pnp 4e.6 off end			# GPIO
-					device pnp 4e.a off end			# PME
-					device pnp 4e.10 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.11 off			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-				end # f81865f
-			end #LPC
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on  end # USB 2
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB3
-			device pci 16.2 off end # EHCI USB3
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-			    { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			    { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/south_station/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/south_station/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
deleted file mode 100644
index e290133d92..0000000000
--- a/src/mainboard/amd/south_station/mainboard.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <delay.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**
- * Southstation using SB GPIO 17/18 to control the Red/Green LED
- * These two LEDs can be used to show the OS booting status.
- */
-static void southstation_led_init(void)
-{
-	/* multi-function pins switch to GPIO0-35 */
-	pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1);
-
-	/* select IOMux to function2, corresponds to GPIO */
-	iomux_write8(0x11, (iomux_read8(0x11) & 0xfc) | 2);
-	iomux_write8(0x12, (iomux_read8(0x12) & 0xfc) | 2);
-
-	/* Lighting test */
-	gpio_100_write8(0x11, 0x08); //output high
-	gpio_100_write8(0x12, 0x08);
-	mdelay(100);
-	gpio_100_write8(0x11, 0x48); //output low
-	gpio_100_write8(0x12, 0x48);
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	southstation_led_init();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
deleted file mode 100644
index 9fcecbc6cd..0000000000
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS       Status;
-	MEM_DATA_STRUCT    *MemData;
-	UINT32             GpioMmioAddr;
-	UINT8              Data8;
-	UINT8              TempData8;
-
-	MemData = ConfigPtr;
-
-	Status = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
-
-	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	Data8 |= BIT2 | BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
-
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
-	}
-	return Status;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS            Status;
-	PCIe_SLOT_RESET_INFO    *ResetInfo;
-	UINT32                  GpioMmioAddr;
-	UINT8                   Data8;
-
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	switch (ResetInfo->ResetId) {
-	case 4:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 &= ~(UINT8)BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
-			Data8 |= BIT6;
-			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 6:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 &= ~(UINT8)BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
-			Data8 |= BIT6;
-			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	case 7:
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 &= ~(UINT8)BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
-			Data8 |= BIT6;
-			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return Status;
-}
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
deleted file mode 100644
index 0c20e5fecb..0000000000
--- a/src/mainboard/amd/union_station/Kconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_AMD_UNIONSTATION
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "amd/union_station"
-
-config MAINBOARD_PART_NUMBER
-	default "Unionstation"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-endif # BOARD_AMD_UNIONSTATION
diff --git a/src/mainboard/amd/union_station/Kconfig.name b/src/mainboard/amd/union_station/Kconfig.name
deleted file mode 100644
index 9af3c8270b..0000000000
--- a/src/mainboard/amd/union_station/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AMD_UNIONSTATION
-	bool "Unionstation"
diff --git a/src/mainboard/amd/union_station/Makefile.inc b/src/mainboard/amd/union_station/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/amd/union_station/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c
deleted file mode 100644
index 16b2db2425..0000000000
--- a/src/mainboard/amd/union_station/OemCustomize.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/amd/union_station/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/amd/union_station/acpi/gpe.asl b/src/mainboard/amd/union_station/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/amd/union_station/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl
deleted file mode 100644
index e3a1bec04e..0000000000
--- a/src/mainboard/amd/union_station/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0F	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1A
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xA0
-			CMDB = 0xA0
-			CMDC = 0xA0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xB0
-			CMDB = 0xB0
-			CMDC = 0xB0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/amd/union_station/acpi/routing.asl b/src/mainboard/amd/union_station/acpi/routing.asl
deleted file mode 100644
index 8f8ea45e9e..0000000000
--- a/src/mainboard/amd/union_station/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/amd/union_station/acpi/sata.asl b/src/mainboard/amd/union_station/acpi/sata.asl
deleted file mode 100644
index e924b571cd..0000000000
--- a/src/mainboard/amd/union_station/acpi/sata.asl
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/amd/union_station/acpi/sleep.asl b/src/mainboard/amd/union_station/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/amd/union_station/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/union_station/acpi/superio.asl b/src/mainboard/amd/union_station/acpi/superio.asl
deleted file mode 100644
index 16990d45f4..0000000000
--- a/src/mainboard/amd/union_station/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/amd/union_station/acpi/usb_oc.asl b/src/mainboard/amd/union_station/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/amd/union_station/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/amd/union_station/board_info.txt b/src/mainboard/amd/union_station/board_info.txt
deleted file mode 100644
index 23fc323460..0000000000
--- a/src/mainboard/amd/union_station/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: Union Station
-Category: eval
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/amd/union_station/bootblock.c b/src/mainboard/amd/union_station/bootblock.c
deleted file mode 100644
index ccd8ec1b40..0000000000
--- a/src/mainboard/amd/union_station/bootblock.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-
-void bootblock_mainboard_early_init(void)
-{
-}
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c
deleted file mode 100644
index 453102aa6a..0000000000
--- a/src/mainboard/amd/union_station/buildOpts.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_S3_LATE_RESTORE			FALSE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/amd/union_station/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb
deleted file mode 100644
index 6c88931d17..0000000000
--- a/src/mainboard/amd/union_station/devicetree.cb
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on end # PCIE P2P bridge 0x9604
-			device pci 5.0 on end # PCIE P2P bridge 0x9605
-			device pci 6.0 on end # PCIE P2P bridge 0x9606
-			device pci 7.0 on end # PCIE P2P bridge 0x9607
-			device pci 8.0 on end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # USB
-			device pci 12.1 on end # USB
-			device pci 12.2 on end # USB
-			device pci 13.0 on end # USB
-			device pci 13.1 on end # USB
-			device pci 13.2 on end # USB
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE    0x439c
-			device pci 14.2 on end # HDA    0x4383
-			device pci 14.3 on end # LPC        0x439d
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on  end # USB 2
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB3
-			device pci 16.2 off end # EHCI USB3
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-
-			register "spdAddrLookup" = "
-			{
-			    { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			    { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/amd/union_station/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c
deleted file mode 100644
index e5d576a349..0000000000
--- a/src/mainboard/amd/union_station/irq_tables.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *)(addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum)
-		pirq->checksum = sum;
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
deleted file mode 100644
index 9850a9056f..0000000000
--- a/src/mainboard/amd/union_station/mainboard.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
deleted file mode 100644
index 85a60e251b..0000000000
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-#endif
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
deleted file mode 100644
index ac42bd4f45..0000000000
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS       Status;
-	MEM_DATA_STRUCT    *MemData;
-	UINT32             GpioMmioAddr;
-	UINT8              Data8;
-	UINT8              TempData8;
-
-	MemData = ConfigPtr;
-
-	Status = AGESA_SUCCESS;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-	Data8 |= BIT2+BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-	TempData8 &= 0x03;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-	Data8 |= BIT2+BIT3;
-	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-	TempData8 &= 0x23;
-	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-	/*
-	 * this seems to be just copy-pasted from the AMD reference boards and
-	 * needs some investigation
-	 */
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-		break;
-	case VOLT1_5:
-	default:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-	}
-	/* disable memory clear for boot time reduction */
-	MemData->ParameterListPtr->EnableMemClr = FALSE;
-	return Status;
-}
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
deleted file mode 100644
index 90b457d5e2..0000000000
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_ASROCK_E350M1
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_NUVOTON_NCT5572D
-	select SB_SUPERIO_HWM
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "asrock/e350m1"
-
-config MAINBOARD_PART_NUMBER
-	default "E350M1"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-endif # BOARD_ASROCK_E350M1
diff --git a/src/mainboard/asrock/e350m1/Kconfig.name b/src/mainboard/asrock/e350m1/Kconfig.name
deleted file mode 100644
index a9a6ec506a..0000000000
--- a/src/mainboard/asrock/e350m1/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASROCK_E350M1
-	bool "E350M1"
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
deleted file mode 100644
index 549801d78f..0000000000
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c
deleted file mode 100644
index 30e9f7e5c5..0000000000
--- a/src/mainboard/asrock/e350m1/OemCustomize.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h
deleted file mode 100644
index 5a46df24e7..0000000000
--- a/src/mainboard/asrock/e350m1/OptionsIds.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-#endif
diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl
deleted file mode 100644
index db500c0ee7..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/gpe.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-}	/* End Scope GPE */
diff --git a/src/mainboard/asrock/e350m1/acpi/routing.asl b/src/mainboard/asrock/e350m1/acpi/routing.asl
deleted file mode 100644
index 50cb070e91..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: PCIe */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl
deleted file mode 100644
index 55b1db5b11..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/asrock/e350m1/board_info.txt b/src/mainboard/asrock/e350m1/board_info.txt
deleted file mode 100644
index 76563ca24c..0000000000
--- a/src/mainboard/asrock/e350m1/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: mini
-Board URL: http://www.asrock.com/mb/overview.asp?Model=E350M1
-ROM package: DIP8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
-Release year: 2011
diff --git a/src/mainboard/asrock/e350m1/bootblock.c b/src/mainboard/asrock/e350m1/bootblock.c
deleted file mode 100644
index 210a0143cf..0000000000
--- a/src/mainboard/asrock/e350m1/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5572d/nct5572d.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
deleted file mode 100644
index 1c4d62c250..0000000000
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout
deleted file mode 100644
index c7cd5e6957..0000000000
--- a/src/mainboard/asrock/e350m1/cmos.layout
+++ /dev/null
@@ -1,38 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	2	e	3	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-3	0	Off
-3	1	On
-3	2	Last
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
deleted file mode 100644
index 1fb8b20ca4..0000000000
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ /dev/null
@@ -1,130 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-
-			device pci 1.1 on end # Internal HDMI Audio
-			device pci 4.0 on end # PCIE P2P bridge 0x9604
-			device pci 5.0 off end # PCIE P2P bridge 0x9605
-			device pci 6.0 off end # PCIE P2P bridge 0x9606
-			device pci 7.0 off end # PCIE P2P bridge 0x9607
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # USB
-			device pci 12.2 on end # USB
-			device pci 13.0 on end # USB
-			device pci 13.2 on end # USB
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC
-				chip superio/nuvoton/nct5572d
-					device pnp 2e.0 off end #  FDC; not externally available on the NCT5572D, but on the die
-					device pnp 2e.1 off end #  LPT1; same as FDC
-					device pnp 2e.2 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 off #  IR
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off #  CIR
-						io 0x60 = 0x100
-						irq 0x70 = 0
-					end
-					device pnp 2e.107 off end #  GPIO6
-					device pnp 2e.207 off end #  GPIO7
-					device pnp 2e.307 on #  GPIO8
-						irq 0x23 = 0x28
-						irq 0xe4 = 0xbf
-						irq 0xed = 0x27
-					end
-					device pnp 2e.407 off end #  GPIO9
-					device pnp 2e.8 off end #  WDT
-					device pnp 2e.009 on #  GPIO2
-						irq 0x2a = 0x42
-						irq 0xe0 = 0xe3
-					end
-					device pnp 2e.109 off end #  GPIO3
-					device pnp 2e.209 off end #  GPIO4
-					device pnp 2e.309 off end #  GPIO5
-					device pnp 2e.a on #  ACPI
-						irq 0xe7 = 0x10
-					end
-					device pnp 2e.b on #  HW Monitor
-						io 0x60 = 0x290
-						io 0x62 = 0x0000 #  SB-TSI currently not implemented
-						irq 0x70 = 5
-					end
-					device pnp 2e.c off end #  PECI
-					device pnp 2e.d on #  SUSLED
-						irq 0xec = 0x90
-					end
-					device pnp 2e.e off #  CIRWKUP
-						io 0x60 = 0x0000
-						irq 0x70 = 0
-					end
-					device pnp 2e.f off end #  GPIO_PP_OD
-				end
-			end #LPC
-			device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on end # USB 2
-			device pci 15.0 on  end # PCIe PortA
-			device pci 15.1 on  end # PCIe PortB: NIC
-			device pci 15.2 on  end # PCIe PortC: USB3
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 on end # OHCI mPCIe
-			device pci 16.2 on end # EHCI mPCIe
-
-			# gpp_configuration options
-			#0000: PortA lanes[3:0]
-			#0001: N/A
-			#0010: PortA lanes[1:0], PortB lanes[3:2]
-			#0011: PortA lanes[1:0], PortB lane2, PortC lane3
-			#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
-			register "gpp_configuration" = "4"
-
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl
deleted file mode 100644
index 226728052f..0000000000
--- a/src/mainboard/asrock/e350m1/dsdt.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-		}
-	}   /* End Scope(_SB)  */
-
-	#include "acpi/superio.asl"
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/asrock/e350m1/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
deleted file mode 100644
index 68255f9946..0000000000
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <device/mmio.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	/* Power off unused clock pins of GPP PCIe devices
-	 * GPP CLK0 connected to unpopulated mini PCIe slot
-	 * GPP CLK1 connected to ethernet chip
-	 */
-	misc_write8(0, 0xff);
-	/* GPP CLK2 connected to the external USB3 controller */
-	misc_write8(1, 0x0f);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	/* SLT_GFX_CLK connected to PCIe slot */
-	misc_write8(4, 0xf0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
deleted file mode 100644
index 6994575985..0000000000
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x1F
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-/**
- * @def SIO_HWM_BASE_ADDRESS
- *    Super IO HWM base address
- */
-#define SIO_HWM_BASE_ADDRESS		0x290
-
-#endif
diff --git a/src/mainboard/elmex/Kconfig b/src/mainboard/elmex/Kconfig
deleted file mode 100644
index cfa52ef0ae..0000000000
--- a/src/mainboard/elmex/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if VENDOR_ELMEX
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/elmex/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/elmex/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	default "ELMEX"
-
-endif # VENDOR_ELMEX
diff --git a/src/mainboard/elmex/Kconfig.name b/src/mainboard/elmex/Kconfig.name
deleted file mode 100644
index b2dcf2e944..0000000000
--- a/src/mainboard/elmex/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_ELMEX
-	bool "ELMEX"
diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
deleted file mode 100644
index 46a33087dc..0000000000
--- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO	*ResetInfo;
-
-	UINT32	GpioMmioAddr;
-	UINT8	 Data8;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	switch (ResetInfo->ResetId)
-	{
-	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
-			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
-			Data8 |= BIT6;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return	Status;
-}
diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig
deleted file mode 100644
index 3845734c93..0000000000
--- a/src/mainboard/elmex/pcm205400/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_ELMEX_PCM205400
-
-config MAINBOARD_PART_NUMBER
-	default "pcm205400"
-
-config VGA_BIOS_ID
-	string
-	default "1002,9806" # FUSION_G_T56N
-
-endif # BOARD_ELMEX_PCM205400
-
-if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F81865F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "elmex/pcm205400"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_ELMEX_PCM205400 | BOARD_ELMEX_PCM205401
diff --git a/src/mainboard/elmex/pcm205400/Kconfig.name b/src/mainboard/elmex/pcm205400/Kconfig.name
deleted file mode 100644
index 445b58868a..0000000000
--- a/src/mainboard/elmex/pcm205400/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ELMEX_PCM205400
-	bool "pcm205400"
diff --git a/src/mainboard/elmex/pcm205400/Makefile.inc b/src/mainboard/elmex/pcm205400/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/elmex/pcm205400/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c
deleted file mode 100644
index 7fc9e0569d..0000000000
--- a/src/mainboard/elmex/pcm205400/OemCustomize.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 46)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/elmex/pcm205400/OptionsIds.h b/src/mainboard/elmex/pcm205400/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/elmex/pcm205400/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/elmex/pcm205400/acpi/gpe.asl b/src/mainboard/elmex/pcm205400/acpi/gpe.asl
deleted file mode 100644
index 705abf17f6..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/gpe.asl
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/elmex/pcm205400/acpi/ide.asl b/src/mainboard/elmex/pcm205400/acpi/ide.asl
deleted file mode 100644
index fec295571d..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0f	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0, Serialized)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1a
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, Serialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xa0
-			CMDB = 0xa0
-			CMDC = 0xa0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF, 0, Serialized) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xb0
-			CMDB = 0xb0
-			CMDC = 0xb0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/elmex/pcm205400/acpi/routing.asl b/src/mainboard/elmex/pcm205400/acpi/routing.asl
deleted file mode 100644
index 656a0be1ee..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/routing.asl
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },	/* Dev 12, INTA, handled by INTC device, Global */
-		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/elmex/pcm205400/acpi/sata.asl b/src/mainboard/elmex/pcm205400/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/elmex/pcm205400/acpi/sleep.asl b/src/mainboard/elmex/pcm205400/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/elmex/pcm205400/acpi/superio.asl b/src/mainboard/elmex/pcm205400/acpi/superio.asl
deleted file mode 100644
index d2d8a44c23..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl b/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/elmex/pcm205400/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/elmex/pcm205400/board_info.txt b/src/mainboard/elmex/pcm205400/board_info.txt
deleted file mode 100644
index e73423fdb5..0000000000
--- a/src/mainboard/elmex/pcm205400/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: PCM205400
-Category: sbc
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/elmex/pcm205400/bootblock.c b/src/mainboard/elmex/pcm205400/bootblock.c
deleted file mode 100644
index 8dca363116..0000000000
--- a/src/mainboard/elmex/pcm205400/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81865f/f81865f.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/elmex/pcm205400/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout
deleted file mode 100644
index fbfe445741..0000000000
--- a/src/mainboard/elmex/pcm205400/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	r	0	reboot_bits
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb
deleted file mode 100644
index bce8a2224a..0000000000
--- a/src/mainboard/elmex/pcm205400/devicetree.cb
+++ /dev/null
@@ -1,136 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge on-board NIC
-			device pci 5.0 off end # PCIE P2P bridge
-			device pci 6.0 on end # PCIE P2P bridge PCIe slot
-			device pci 7.0 off end # PCIE P2P bridge
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 on end # IDE	0x439c
-			device pci 14.2 off end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/fintek/f81865f
-					device pnp 4e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 4e.3 off end			# Parallel Port
-					device pnp 4e.4 off end			# Hardware Monitor
-					device pnp 4e.5 off end			# Keyboard
-					device pnp 4e.6 off end			# GPIO
-					device pnp 4e.a off end			# PME
-					device pnp 4e.10 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.11 on			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-				end # f81865f
-			end #LPC
-			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 off end # OHCI FS/LS USB
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 off end # OHCI USB 10-13
-			device pci 16.2 off end # EHCI USB 10-13
-
-			register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-
-			#set up SB800 Fan control registers and IMC fan controls
-			register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
-			register "fan0_enabled" = "1"
-			register "fan1_enabled" = "1"
-			register "imc_fan_zone0_enabled" = "1"
-			register "imc_fan_zone1_enabled" = "1"
-
-			register "fan0_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-			register "fan1_config_vals" = "{ \
-				FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-				FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
-			register "imc_zone0_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
-			register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone0_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone0_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone0_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone0_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone0_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			register "imc_zone1_mode1" = " \
-				IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-				IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
-			register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-				IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-			register "imc_zone1_temp_offset" = "0x00"	# No temp offset
-			register "imc_zone1_hysteresis" = "0x05"	# Degrees C Hysteresis
-			register "imc_zone1_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-			register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-			register "imc_zone1_pwm_step" = "0x01"		# Fan PWM stepping rate
-			register "imc_zone1_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-			# T56N has a Maximum operating temperature  of 90C
-			# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
-			# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
-			register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
-			register "imc_zone0_fanspeeds"  = "{100,  7,  5,  4,  3, 2, 0, 0 }"
-			register "imc_zone1_thresholds" = "{ 85, 80, 75, 65,  1, 0, 0, 0, 90 }"
-			register "imc_zone1_fanspeeds"  = "{100, 10,  6,  4,  3, 0, 0, 0 }"
-
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/elmex/pcm205400/dsdt.asl b/src/mainboard/elmex/pcm205400/dsdt.asl
deleted file mode 100644
index 834a2cfbf9..0000000000
--- a/src/mainboard/elmex/pcm205400/dsdt.asl
+++ /dev/null
@@ -1,50 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/elmex/pcm205400/irq_tables.c b/src/mainboard/elmex/pcm205400/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/elmex/pcm205400/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c
deleted file mode 100644
index e7ca602a90..0000000000
--- a/src/mainboard/elmex/pcm205400/mainboard.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/device.h>
-#include <device/mmio.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/cimx/sb800/pci_devs.h>
-#include <northbridge/amd/agesa/family14/pci_devs.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- *
- * The Persimmon PCI INTA/B/C/D pins are connected to
- * FCH pins INTE/F/G/H on the schematic so these need
- * to be routed as well.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
-	/* IDE, SATA */
-	[0x40] = 0x0B,0x0B,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x0A,0x0B,0x0A,0x0B
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
-	/* IDE, SATA */
-	[0x40] = 0x11,0x13,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x10,0x11,0x12,0x13
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-/*
- * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isn't implemented to match
- * the IDSEL (dev 3) of the slot, the table is adjusted for the
- * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
- * off-chip devices should get mapped to PIRQH/E/F/G.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
-	{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
-	{IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
-	{OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* enable GPP CLK0 thru CLK1 */
-	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	misc_write8(0, 0xff);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/elmex/pcm205400/platform_cfg.h b/src/mainboard/elmex/pcm205400/platform_cfg.h
deleted file mode 100644
index 7926249ff0..0000000000
--- a/src/mainboard/elmex/pcm205400/platform_cfg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x07
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-static const CODECENTRY persimmon_codec_alc269[] = {
-	/* NID, PinConfig */
-	{0x12, 0x411111F0},
-	{0x14, 0x99130110},
-	{0x21, 0x0121401F},
-	{0x17, 0x411111F0},
-	{0x18, 0x01A19820},
-	{0x19, 0x411111F0},
-	{0x1A, 0x0181302F},
-	{0x1B, 0x411111F0},
-	{0x1D, 0x40069E05},
-	{0x1E, 0x411111F0},
-	{0x20, 0x0001FFFF},
-	{0xff, 0xffffffff} /* end of table */
-};
-
-static const CODECTBLLIST codec_tablelist[] = {
-	{0x010ec0269, (CODECENTRY *)&persimmon_codec_alc269[0]},
-	{0x0FFFFFFFFUL, (CODECENTRY *)0x0FFFFFFFFUL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-//#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig
deleted file mode 100644
index ca085ac33b..0000000000
--- a/src/mainboard/elmex/pcm205401/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# The code for this board is under elmex/pcm205400
-
-if BOARD_ELMEX_PCM205401
-
-config MAINBOARD_PART_NUMBER
-	default "pcm205401"
-
-config VGA_BIOS_ID
-	string
-	default "1002,9804" # FUSION_G_T40R
-
-endif # BOARD_ELMEX_PCM205401
diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name
deleted file mode 100644
index eb14caca73..0000000000
--- a/src/mainboard/elmex/pcm205401/Kconfig.name
+++ /dev/null
@@ -1,4 +0,0 @@
-# The code for this board is under elmex/pcm205400
-
-config BOARD_ELMEX_PCM205401
-	bool "pcm205401"
diff --git a/src/mainboard/elmex/pcm205401/board_info.txt b/src/mainboard/elmex/pcm205401/board_info.txt
deleted file mode 100644
index 4d51c8f09b..0000000000
--- a/src/mainboard/elmex/pcm205401/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: PCM205401
-Category: sbc
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
deleted file mode 100644
index fee293f0b0..0000000000
--- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd_from_cbfs },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	// Unlike AMD/Inagua, this board is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig
deleted file mode 100644
index b70b7f3ca1..0000000000
--- a/src/mainboard/gizmosphere/gizmo/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_GIZMOSPHERE_GIZMO
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-	select HAVE_SPD_IN_CBFS
-
-config MAINBOARD_DIR
-	default "gizmosphere/gizmo"
-
-config MAINBOARD_PART_NUMBER
-	default "Gizmo"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9804"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-config DIMM_SPD_SIZE
-	default 128
-
-endif # BOARD_GIZMOSPHERE_GIZMO
diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig.name b/src/mainboard/gizmosphere/gizmo/Kconfig.name
deleted file mode 100644
index 97c1f79da1..0000000000
--- a/src/mainboard/gizmosphere/gizmo/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GIZMOSPHERE_GIZMO
-	bool "Gizmo"
diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc
deleted file mode 100644
index 2d5aa7552d..0000000000
--- a/src/mainboard/gizmosphere/gizmo/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = Elpida_EDJ2116DEBG
diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c
deleted file mode 100644
index a969eea087..0000000000
--- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
-
-	// Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
-	// Gizmos soldered down memory requires different seeds
-#define WLSEED 0x08
-#define RXSEED 0x40
-	WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
-	HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
-
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h
deleted file mode 100644
index 954ef21e58..0000000000
--- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-#endif
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl b/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl
deleted file mode 100644
index 44e7b68eac..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl b/src/mainboard/gizmosphere/gizmo/acpi/ide.asl
deleted file mode 100644
index 61c2fcfbb8..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/ide.asl
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Local0 = Arg0 & 0x0f	/* Recovery Width */
-	Local0++
-	Local1 = Arg0 >> 4	/* Command Width */
-	Local1++
-	Return(30 * (Local0 + Local1))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If (PPCR & 0x01) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		BFFG |= 0x1a
-
-		PSD0 = GTTM (PPTM) /* save total time of primary PIO master timing  to PIO spd0 */
-		PSD1 = GTTM (PPTS) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If (PDCR & 0x01) {	/* It's under UDMA mode */
-			BFFG |= 0x01
-			DSD0 = DerefOf(UDTT [PDMM])
-		}
-		Else {
-			DSD0 = GTTM (PMTM) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If (PDCR & 0x02) {	/* It's under UDMA mode */
-			BFFG |= 0x04
-			DSD1 = DerefOf(UDTT [PDSM])
-		}
-		Else {
-			DSD1 = GTTM (PMTS) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, NotSerialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Local0 = Match (POTT, MLE, PSD0, MTR, 0, 0)
-		PPMM = Local0 % 5 /* Primary PIO master Mode */
-		Local1 = Match (POTT, MLE, PSD1, MTR, 0, 0)
-		PPSM = Local1 % 5 /* Primary PIO slave Mode */
-
-		PPTM = DerefOf(PORT [Local0]) /* Primary PIO Master Timing */
-		PPTS = DerefOf(PORT [Local1]) /* Primary PIO Slave Timing */
-
-		If (BFFG & 0x01) {	/* Drive 0 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD0, MTR, 0, 0)
-			PDMM = Local0 % 7
-			PDCR |= 0x01
-		}
-		Else {
-			If (DSD0 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD0, MTR, 0, 0)
-				PMTM = DerefOf(MDRT [Local0])
-			}
-		}
-
-		If (BFFG & 0x04) {	/* Drive 1 is under UDMA mode */
-			Local0 = Match (UDTT, MLE, DSD1, MTR, 0, 0)
-			PDSM = Local0 % 7
-			PDCR |= 0x02
-		}
-		Else {
-			If (DSD1 != 0xFFFFFFFF) {
-				Local0 = Match (MDTT, MLE, DSD1, MTR, 0, 0)
-				PMTS = DerefOf(MDRT [Local0])
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xa0
-			CMDB = 0xa0
-			CMDC = 0xa0
-
-			POMD = PPMM | 0x08
-
-			If (PDCR & 0x01) {
-				DMMD = PDMM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTM), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			CMDA = 0xb0
-			CMDB = 0xb0
-			CMDC = 0xb0
-
-			POMD = PPSM | 0x08
-
-			If (PDCR & 0x02) {
-				DMMD = PDSM | 0x40
-			}
-			Else {
-				Local0 = Match (MDTT, MLE, GTTM(PMTS), MTR, 0, 0)
-				If (Local0 < 3) {
-					DMMD = Local0 | 0x20
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl b/src/mainboard/gizmosphere/gizmo/acpi/routing.asl
deleted file mode 100644
index 50cb070e91..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/routing.asl
+++ /dev/null
@@ -1,382 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: PCIe */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl b/src/mainboard/gizmosphere/gizmo/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl b/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl b/src/mainboard/gizmosphere/gizmo/acpi/superio.asl
deleted file mode 100644
index d2d8a44c23..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl b/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/gizmosphere/gizmo/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/gizmosphere/gizmo/board_info.txt b/src/mainboard/gizmosphere/gizmo/board_info.txt
deleted file mode 100644
index 7680e6f854..0000000000
--- a/src/mainboard/gizmosphere/gizmo/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: half
diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/gizmosphere/gizmo/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/gizmosphere/gizmo/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb
deleted file mode 100644
index f7e9a0184e..0000000000
--- a/src/mainboard/gizmosphere/gizmo/devicetree.cb
+++ /dev/null
@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-			chip cpu/amd/agesa/family14
-				device lapic 0 on end
-			end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-			chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-			chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-				device pci 0.0 on end # Root Complex
-				device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-				device pci 4.0 off end # PCIE P2P bridge 0x9604
-				device pci 5.0 on end # PCIE P2P bridge 0x9605
-				device pci 6.0 off end # PCIE P2P bridge 0x9606
-				device pci 7.0 off end # PCIE P2P bridge 0x9607
-				device pci 8.0 off end # NB/SB Link P2P bridge
-			end # agesa northbridge
-
-			chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus
-				device pci 11.0 on end # SATA
-				device pci 12.0 on end # USB
-				device pci 12.1 on end # USB
-				device pci 12.2 on end # USB
-				device pci 13.0 on end # USB
-				device pci 13.1 on end # USB
-				device pci 13.2 on end # USB
-				device pci 14.0 on end # SM
-				device pci 14.1 on end # IDE	0x439c
-				device pci 14.2 on end # HDA	0x4383
-				device pci 14.3 on end # LPC	0x439d
-				device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
-				device pci 14.5 off end # USB 2
-				device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
-				device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector
-				device pci 16.0 off end # OHCI USB3
-				device pci 16.2 off end # EHCI USB3
-				register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
-				register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
-			end	#southbridge/amd/cimx/sb800
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl
deleted file mode 100644
index ea60c1cdb7..0000000000
--- a/src/mainboard/gizmosphere/gizmo/dsdt.asl
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/gizmosphere/gizmo/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c
deleted file mode 100644
index c50f4b935e..0000000000
--- a/src/mainboard/gizmosphere/gizmo/mainboard.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <delay.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <device/pci_ops.h>
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	pirq_setup();
-
-	/* enable GPP CLK0 thru CLK1 */
-	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	misc_write8(0, 0xFF);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Force the onboard SATA port to GEN2 speed.
-	 * The offboard SATA port can remain at GEN3.
-	 */
-	pm_write8(0xda, (pm_read8(0xda) & 0xfb) | 0x04);
-}
-
-static void mainboard_final(void *chip_info)
-{
-	struct device *ahci_dev;
-	uintptr_t ABAR;
-	u8 *memptr;
-
-	ahci_dev = pcidev_on_root(0x11, 0);
-	ABAR = pci_read_config32(ahci_dev, 0x24);
-	ABAR &= 0xFFFFFC00;
-	memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */
-	*memptr = 0x21; /* force to GEN2 and start re-negotiate */
-	mdelay(1);
-	*memptr = 0x20;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-	.final = mainboard_final,
-};
diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h
deleted file mode 100644
index af7da08234..0000000000
--- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/* Gizmo has no legacy P/S2 controller */
-#define LEGACY_FREE		1
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x00 /* PCI clocks aren't used on Gizmo */
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		TRUE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-static const CODECENTRY gizmo_codec_alc272[] =
-{
-	/* NID, PinConfig */
-	{0x11, 0x411111F0},	/* S/PDIF-OUT2 unused */
-	{0x12, 0x411111F0},	/* DMIC-1/2 unused */
-	{0x13, 0x411111F0},	/* DMIC-3/4 unused */
-	{0x14, 0x411111F0},	/* LOUT-1 unused */
-	{0x15, 0x21000100},	/* LOUT2 - to Explorer */
-	{0x17, 0x411111F0},	/* MONO-OUT unused */
-	{0x18, 0x01A15010},	/* MIC1 */
-	{0x19, 0x411111F0},	/* MIC2 unused */
-	{0x1A, 0x01013010},	/* LINE1 */
-	{0x1B, 0x21800101},	/* LINE2 from Explorer */
-	{0x1D, 0x40100000},	/* PCBEEP */
-	{0x1E, 0x411111F0},	/* S/PDIF-OUT1 unused */
-	{0x21, 0x01214010},	/* HPOUT */
-	{0xff, 0xffffffff}	/* end of table */
-};
-
-static const CODECTBLLIST codec_tablelist[] =
-{
-	{0x010ec0272, (CODECENTRY*)&gizmo_codec_alc272[0]},
-	{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif
diff --git a/src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex b/src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex
deleted file mode 100644
index 5b3b94ed9d..0000000000
--- a/src/mainboard/gizmosphere/gizmo/spd/Elpida_EDJ2116DEBG.spd.hex
+++ /dev/null
@@ -1,252 +0,0 @@
-# Elpida EDJ2116DEBG 2Gb
-
-#	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-#		bits[3:0]: 1 = 128 SPD Bytes Used
-#		bits[6:4]: 1 = 256 SPD Bytes Total
-#		bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-#	1 SPD Revision
-#		0x10 = Revision 1.0
-10
-
-#	2 Key Byte / DRAM Device Type
-#		bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-#	3 Key Byte / Module Type
-#		bits[3:0]: 3 = SO-DIMM
-#		bits[7:4]: reserved
-03
-
-#	4 SDRAM CHIP Density and Banks
-#		bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-#		bits[6:4]: 0 = 3 (8 banks)
-#		bit7 : reserved
-03
-
-#	5 SDRAM Addressing
-#		bits[2:0]: 1 = 10 Column Address Bits
-#		bits[5:3]: 2 = 14 Row Address Bits
-#		bits[7:6]: reserved
-11
-
-#	6 Module Nominal Voltage, VDD
-#		bit0 : 0 = 1.5 V operable
-#		bit1 : 0 = NOT 1.35 V operable
-#		bit2 : 0 = NOT 1.25 V operable
-#		bits[7:3]: reserved
-00
-
-#	7 Module Organization
-#		bits[2:0]: 2 = 16 bits
-#		bits[5:3]: 0 = 1 Rank
-#		bits[7:6]: reserved
-02
-
-#	8 Module Memory Bus Width
-#		bits[2:0]: 3 = Primary bus width is 64 bits
-#		bits[4:3]: 0 = 0 bits (no bus width extension)
-#		bits[7:5]: reserved
-03
-
-#	9 Fine Timebase (FTB) Dividend / Divisor
-#		bits[3:0]: 0x02 divisor
-#		bits[7:4]: 0x05 dividend
-#		5 / 2 = 2.5ps
-52
-
-#	10 Medium Timebase (MTB) Dividend
-#	11 Medium Timebase (MTB) Divisor
-#		1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
-01 08
-
-#	12 SDRAM Minimum Cycle Time (tCKmin)
-#		0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
-#		0x0c = tCKmin of 1.25 ns = DDR3-1333 (667 MHz clock)
-0C
-
-#	13 Reserved
-00
-
-#	14 CAS Latencies Supported, Least Significant Byte
-#		0xfc = CL 6,7,8,9,10,11
-#		0xfe = CL 5,6,7,8,9,10,11
-#	15 CAS Latencies Supported, Most Significant Byte
-#		Cas Latencies of 11 - 5 are supported
-FC 00
-
-#	16 Minimum CAS Latency Time (tAAmin)
-#		0x69 = 13.125ns
-#		0x6E = 13.75ns - DDR3-1600K
-69
-
-#	17 Minimum Write Recovery Time (tWRmin)
-#		0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-#	18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-#		0x69 = 13.125ns
-#		0x6E = 13.75ns - DDR3-1600K
-69
-
-#	19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-#		0x38 = 7.0ns
-#		0x3C = 7.5ns
-38
-
-#	20 Minimum Row Precharge Delay Time (tRPmin)
-#		0x69 = 13.125ns -
-#		0x6E = 13.75ns - DDR3-1600K
-69
-
-#	21 Upper Nibbles for tRAS and tRC
-#		bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-#		bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-#	22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-#		0x118 = 35ns - DDR3-1600 (see byte 21)
-#		0x120 = 36ns - DDR3
-20
-
-#	23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-#		0x186 = 48.75ns - DDR3-1600K
-#		0x189 = 49.125ns - DDR3-
-89
-
-#	24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-#	25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-#		0x500 = 160ns - for 2 Gigabit chips
-00 05
-
-#	26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-#		0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-#	27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-#		0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-#	28 Upper Nibble for tFAWmin
-#	29 Minimum Four Activate Window Delay Time (tFAWmin)
-#		0x0140 = 40ns - DDR3-1600, 2 KB page size
-#		0x0168 = 45ns - DDR3- , 2 KB page size
-01 68
-
-#	30 SDRAM Optional Feature
-#		bit0 : 1= RZQ/6 supported
-#		bit1 : 1 = RZQ/7 supported
-#		bits[6:2]: reserved
-#		bit7 : 1 = DLL Off mode supported
-83
-
-#	31 SDRAM Thermal and Refresh Options
-#		bit0 : 1 = Temp up to 95c supported
-#		bit1 : 0 = 85-95c uses 2x refresh rate
-#		bit2 : 1 = Auto Self Refresh supported
-#		bit3 : 0 = no on die thermal sensor
-#		bits[6:4]: reserved
-#		bit7 : 0 = partial self refresh supported
-05
-
-#	32 Module Thermal Sensor
-#		0 = Thermal sensor not incorporated onto this assembly
-00
-
-#	33 SDRAM Device Type
-#		bits[1:0]: 0 = Signal Loading not specified
-#		bits[3:2]: reserved
-#		bits[6:4]: 0 = Die count not specified
-#		bit7 : 0 = Standard Monolithic DRAM Device
-00
-
-#	34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-00
-
-#	35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-00
-
-#	36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-00
-
-#	37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-00
-
-#	38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00
-
-#	39 (reserved)
-00
-
-#	40 - 47 (reserved)
-00 00 00 00 00 00 00 00
-
-#	48 - 55 (reserved)
-00 00 00 00 00 00 00 00
-
-#	56 - 59 (reserved)
-00 00 00 00
-
-#	60 Raw Card Extension, Module Nominal Height
-#		bits[4:0]: 0 = <= 15mm tall
-#		bits[7:5]: 0 = raw card revision 0-3
-00
-
-#	61 Module Maximum Thickness
-#		bits[3:0]: 0 = thickness front <= 1mm
-#		bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-#	62 Reference Raw Card Used
-#		bits[4:0]: 0 = Reference Raw card A used
-#		bits[6:5]: 0 = revision 0
-#		bit7 : 0 = Reference raw cards A through AL
-00
-
-#	63 Address Mapping from Edge Connector to DRAM
-#		bit0 : 0 = standard mapping (not mirrored)
-#		bits[7:1]: reserved
-00
-
-#	64 - 71 (reserved)
-00 00 00 00 00 00 00 00
-
-#	72 - 79 (reserved)
-00 00 00 00 00 00 00 00
-
-#	80 - 87 (reserved)
-00 00 00 00 00 00 00 00
-
-#	88 - 95 (reserved)
-00 00 00 00 00 00 00 00
-
-#	96 - 103 (reserved)
-00 00 00 00 00 00 00 00
-
-#	104 - 111 (reserved)
-00 00 00 00 00 00 00 00
-
-#	112 - 116 (reserved)
-00 00 00 00 00
-
-#	117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-#		0x0001 = AMD
-00 01
-
-#	119 Module ID: Module Manufacturing Location - OEM specified
-00
-
-#	120 Module ID: Module Manufacture Year in BCD
-#		0x13 = 2013
-13
-
-#	121 Module ID: Module Manufacture week
-#		0x12 = 12th week
-12
-
-#	122 - 125: Module Serial Number
-53 41 47 45
-
-#	126 - 127: Cyclical Redundancy Code
-9D A6
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
deleted file mode 100644
index 93cac46a64..0000000000
--- a/src/mainboard/jetway/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if VENDOR_JETWAY
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/jetway/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/jetway/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	default "Jetway"
-
-endif # VENDOR_JETWAY
diff --git a/src/mainboard/jetway/Kconfig.name b/src/mainboard/jetway/Kconfig.name
deleted file mode 100644
index 30128391e2..0000000000
--- a/src/mainboard/jetway/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_JETWAY
-	bool "Jetway"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
deleted file mode 100644
index f8a48b8d2d..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-
-#include <amdlib.h>
-#include <amdblocks/acpimmio.h>
-#include <vendorcode/amd/cimx/sb800/SB800.h>
-#include <stdint.h>
-
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		board_GnbPcieSlotReset },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	/* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	 * Make sure the right speed settings are selected.
-	 */
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
-
-/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_STATUS Status;
-	PCIe_SLOT_RESET_INFO	*ResetInfo;
-
-	uint32_t	GpioMmioAddr;
-	uint8_t	 Data8;
-
-	ResetInfo = ConfigPtr;
-	Status = AGESA_UNSUPPORTED;
-	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
-	switch (ResetInfo->ResetId)
-	{
-	case 46:	/* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
-		switch (ResetInfo->ResetControl) {
-		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
-			Data8 &= ~(uint8_t)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
-			Data8 |= BIT6;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
-			Status = AGESA_SUCCESS;
-			break;
-		}
-		break;
-	}
-	return	Status;
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
deleted file mode 100644
index e1eec04fe5..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_JETWAY_NF81_T56N_LF
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_FINTEK_F71869AD
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_2048
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "jetway/nf81-t56n-lf"
-
-config MAINBOARD_PART_NUMBER
-	default "NF81-T56N-LF"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9806" # FUSION_G_T56N
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
deleted file mode 100644
index 2e660f937c..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_JETWAY_NF81_T56N_LF
-	bool "NF81_T56N_LF"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
deleted file mode 100644
index 9655909056..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c b/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
deleted file mode 100644
index 3f420c0d34..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled,
-						ChannelTypeExt6db,
-						4,
-						HotplugDisabled,
-						PcieGen2,
-						PcieGen2,
-						AspmL0sL1,
-						46)
-	},
-	/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled,
-						ChannelTypeExt6db,
-						5,
-						HotplugDisabled,
-						PcieGen2,
-						PcieGen2,
-						AspmL0sL1,
-						46)
-	},
-	/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled,
-						ChannelTypeExt6db,
-						6,
-						HotplugDisabled,
-						PcieGen2,
-						PcieGen2,
-						AspmL0sL1,
-						46)
-	},
-	/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled,
-						ChannelTypeExt6db,
-						7,
-						HotplugDisabled,
-						PcieGen2,
-						PcieGen2,
-						AspmL0sL1,
-						0)
-	},
-	/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled,
-						ChannelTypeExt6db,
-						8,
-						HotplugDisabled,
-						PcieGen2,
-						PcieGen2,
-						AspmL0sL1,
-						0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* (DDI interface Lanes 8:11, DdA, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */
-		{ConnectorTypeLvds, Aux1, Hdp1}
-	},
-	/* (DDI interface Lanes 12:15, DdB, ...) */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		/* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */
-		{ConnectorTypeDP, Aux2, Hdp2}
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/**
- * @brief Customer Overrides Memory Table
- *
- * Platform Specific Overriding Table allows IBV/OEM to pass in platform
- * information to AGESA
- * (e.g. MemClk routing, the number of DIMM slots per channel,...).
- * If PlatformSpecificTable is populated, AGESA will base its settings on the
- * data from the table. Otherwise, it will use its default conservative settings.
- */
-static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h b/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl
deleted file mode 100644
index 705abf17f6..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl
deleted file mode 100644
index 656a0be1ee..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/routing.asl
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },	/* Dev 12, INTA, handled by INTC device, Global */
-		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl
deleted file mode 100644
index 55b1db5b11..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
deleted file mode 100644
index a5ec36e585..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF
-Category: mini
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
-Release year: 2011
diff --git a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c
deleted file mode 100644
index c4bcd21eee..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/bootblock.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f71869ad/f71869ad.h>
-
-/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
-#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
deleted file mode 100644
index f2342510f8..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ /dev/null
@@ -1,128 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge PCIe slot
-			device pci 5.0 off end # PCIE P2P bridge
-			device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
-			device pci 7.0 off end # PCIE P2P bridge
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 off end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/fintek/f71869ad
-					register "multi_function_register_1" = "0x01"
-					register "multi_function_register_2" = "0x6f"
-					register "multi_function_register_3" = "0x24"
-					register "multi_function_register_4" = "0x00"
-					register "multi_function_register_5" = "0x60"
-# HWM configuration registers
-					register "hwm_smbus_address" = "0x98"
-					register "hwm_smbus_control_reg" = "0x02"
-					register "hwm_fan_type_sel_reg" = "0x00"
-					register "hwm_fan1_temp_adj_rate_reg" = "0x33"
-					register "hwm_fan_mode_sel_reg" = "0x07"
-					register "hwm_fan1_idx_rpm_mode" = "0x0e"
-					register "hwm_fan1_seg1_speed_count" = "0xff"
-					register "hwm_fan1_seg2_speed_count" = "0x0e"
-					register "hwm_fan1_seg3_speed_count" = "0x07"
-					register "hwm_fan1_temp_map_sel" = "0x8c"
-					register "hwm_temp_sensor_type" = "0x0E"	# default value
-#
-# XXX: 4e is the default index port and .xy is the
-# LDN indexing the pnp_info array found in the superio.c
-# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
-#     see page 18 from Fintek F71869 V1.1 datasheet.
-					device pnp 2e.00 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.01 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-# COM2 not physically wired on board.
-					device pnp 2e.02 off		# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.03 off		# Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-						drq 0x74 = 3
-					end
-					device pnp 2e.04 on			# Hardware Monitor
-						io 0x60 = 0x225 # Fintek datasheet says 0x295.
-						irq 0x70 = 0
-					end
-					device pnp 2e.05 on # KBC
-						io 0x60 = 0x060
-						irq 0x70 = 1 # Keyboard IRQ
-						irq 0x72 = 12 # Mouse IRQ
-					end
-					device pnp 2e.06 off end	# GPIO
-					device pnp 2e.07 on end	# WDT
-					device pnp 2e.08 off end	# CIR
-					device pnp 2e.0a on end	# PME
-				end # f71869ad
-			end #LPC
-			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 on end # OHCI FS/LS USB (0x4399)
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
-			device pci 15.1 on end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 on end # OHCI USB 10-13 (0x4397)
-			device pci 16.2 on end # EHCI USB 10-13 (0x4396)
-			register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes.
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-#
-# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
-# with i2cdump tool.
-# Notes:  0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
-#
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
deleted file mode 100644
index 5feb9f277e..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-
-	#include "acpi/superio.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
deleted file mode 100644
index 2ffea02c84..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align table on 16 byte boundary. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* PCI Bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
deleted file mode 100644
index 53cb8c3e60..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <device/device.h>
-
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/cimx/sb800/pci_devs.h>
-#include <northbridge/amd/agesa/family14/pci_devs.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- *
- * The Persimmon PCI INTA/B/C/D pins are connected to
- * FCH pins INTE/F/G/H on the schematic so these need
- * to be routed as well.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
-	/* IDE, SATA */
-	[0x40] = 0x0B,0x0B,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x0A,0x0B,0x0A,0x0B
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
-	/* IDE, SATA */
-	[0x40] = 0x11,0x13,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x10,0x11,0x12,0x13
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-/*
- * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isn't implemented to match
- * the IDSEL (dev 3) of the slot, the table is adjusted for the
- * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
- * off-chip devices should get mapped to PIRQH/E/F/G.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
-	{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* PCIe bdg:  06.0 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
-	{IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
-	{OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* enable GPP CLK0 thru CLK3 (interleaved) */
-	/* disable GPP CLK4 thru SLT_GFX_CLK */
-	misc_write8(0, 0xff);
-	misc_write8(1, 0xff);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code. The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
deleted file mode 100644
index 9c8d0f6e47..0000000000
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x07
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-/* FIXME: Verify this for sound to work! */
-static const CODECENTRY persimmon_codec_alc269[] =
-{
-	/* NID, PinConfig */
-	{0x12, 0x411111F0},
-	{0x14, 0x99130110},
-	{0x21, 0x0121401F},
-	{0x17, 0x411111F0},
-	{0x18, 0x01A19820},
-	{0x19, 0x411111F0},
-	{0x1A, 0x0181302F},
-	{0x1B, 0x411111F0},
-	{0x1D, 0x40069E05},
-	{0x1E, 0x411111F0},
-	{0x20, 0x0001FFFF},
-	{0xff, 0xffffffff} /* end of table */
-};
-
-/* FIXME: Verify this for sound to work! */
-static const CODECTBLLIST codec_tablelist[] =
-{
-	{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
-	{0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig
deleted file mode 100644
index 0a9a454b8e..0000000000
--- a/src/mainboard/lippert/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if VENDOR_LIPPERT
-
-comment "was acquired by ADLINK"
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/lippert/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/lippert/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	default "LiPPERT"
-
-endif # VENDOR_LIPPERT
diff --git a/src/mainboard/lippert/Kconfig.name b/src/mainboard/lippert/Kconfig.name
deleted file mode 100644
index 9a0c11cf69..0000000000
--- a/src/mainboard/lippert/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_LIPPERT
-	bool "LiPPERT"
diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig
deleted file mode 100644
index e7472b1853..0000000000
--- a/src/mainboard/lippert/frontrunner-af/Kconfig
+++ /dev/null
@@ -1,61 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_SMSC_SMSCSUPERIO if BOARD_LIPPERT_FRONTRUNNER_AF
-	# The Toucan-AF is meant to work on any COM Express Type 6 baseboard.
-	# The ADLINK ExpressBase-6 baseboard happens to use this SIO:
-	select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
-	# boot, wasting 3 s and causing wear!  Therefore disable S3 for now.
-	#select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_4096
-	select GFXUMA
-
-config MAINBOARD_DIR
-	default "lippert/frontrunner-af"
-
-config VARIANT_DIR
-	default "frontrunner-af" if BOARD_LIPPERT_FRONTRUNNER_AF
-	default "toucan-af"      if BOARD_LIPPERT_TOUCAN_AF
-
-config DEVICETREE
-	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config MAINBOARD_PART_NUMBER
-	default "FrontRunner-AF" if BOARD_LIPPERT_FRONTRUNNER_AF
-	default "Toucan-AF"      if BOARD_LIPPERT_TOUCAN_AF
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig.name b/src/mainboard/lippert/frontrunner-af/Kconfig.name
deleted file mode 100644
index caf65d1e65..0000000000
--- a/src/mainboard/lippert/frontrunner-af/Kconfig.name
+++ /dev/null
@@ -1,5 +0,0 @@
-config BOARD_LIPPERT_FRONTRUNNER_AF
-	bool "FrontRunner-AF aka ADLINK CoreModule2-GF"
-
-config BOARD_LIPPERT_TOUCAN_AF
-	bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)"
diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc
deleted file mode 100644
index b05b4e8bcb..0000000000
--- a/src/mainboard/lippert/frontrunner-af/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += variants/$(VARIANT_DIR)/bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c
-romstage-y += variants/$(VARIANT_DIR)/OemCustomize.c
-
-ramstage-y += buildOpts.c
-ramstage-y += variants/$(VARIANT_DIR)/BiosCallOuts.c
-ramstage-y += variants/$(VARIANT_DIR)/OemCustomize.c
-ramstage-y += variants/$(VARIANT_DIR)/mainboard.c
-
-# Minimal SEMA watchdog support
-romstage-y += sema.c
-ramstage-y += sema.c
diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl b/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
deleted file mode 100644
index 5968ff3294..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/gpe.asl
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-
-		/*  General event 3  */
-		Method(_L03) {
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-		}
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-		}
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-		}
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-	}	/* End Scope GPE */
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl b/src/mainboard/lippert/frontrunner-af/acpi/routing.asl
deleted file mode 100644
index 2820cbbf01..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/routing.asl
+++ /dev/null
@@ -1,402 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		Package(){0x0009FFFF, 0, INTB, 0 },
-		Package(){0x0009FFFF, 1, INTC, 0 },
-		Package(){0x0009FFFF, 2, INTD, 0 },
-		Package(){0x0009FFFF, 3, INTA, 0 },
-
-		Package(){0x000AFFFF, 0, INTC, 0 },
-		Package(){0x000AFFFF, 1, INTD, 0 },
-		Package(){0x000AFFFF, 2, INTA, 0 },
-		Package(){0x000AFFFF, 3, INTB, 0 },
-
-		Package(){0x000BFFFF, 0, INTD, 0 },
-		Package(){0x000BFFFF, 1, INTA, 0 },
-		Package(){0x000BFFFF, 2, INTB, 0 },
-		Package(){0x000BFFFF, 3, INTC, 0 },
-
-		Package(){0x000CFFFF, 0, INTA, 0 },
-		Package(){0x000CFFFF, 1, INTB, 0 },
-		Package(){0x000CFFFF, 2, INTC, 0 },
-		Package(){0x000CFFFF, 3, INTD, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Package(){0x0014FFFF, 1, INTA, 0 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 16 },
-		Package(){0x0009FFFF, 2, 0, 17 },
-		Package(){0x0009FFFF, 3, 0, 18 },
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 16 },
-		Package(){0x000AFFFF, 2, 0, 17 },
-		Package(){0x000AFFFF, 3, 0, 18 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		/* Package(){0x0012FFFF, 2, 0, 18 }, */
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-		/* Package(){0x0013FFFF, 2, 0, 16 }, */
-
-		/* Package(){0x00140000, 0, 0, 16 }, */
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: pcie */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APSA, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-		/* PCI slots: slot 0, slot 1, slot 2, slot 3 behind Dev14, Fun4. */
-		Package(){0x0004FFFF, 0, 0, 0x14 },
-		Package(){0x0004FFFF, 1, 0, 0x15 },
-		Package(){0x0004FFFF, 2, 0, 0x16 },
-		Package(){0x0004FFFF, 3, 0, 0x17 },
-		Package(){0x0005FFFF, 0, 0, 0x15 },
-		Package(){0x0005FFFF, 1, 0, 0x16 },
-		Package(){0x0005FFFF, 2, 0, 0x17 },
-		Package(){0x0005FFFF, 3, 0, 0x14 },
-		Package(){0x0006FFFF, 0, 0, 0x16 },
-		Package(){0x0006FFFF, 1, 0, 0x17 },
-		Package(){0x0006FFFF, 2, 0, 0x14 },
-		Package(){0x0006FFFF, 3, 0, 0x15 },
-		Package(){0x0007FFFF, 0, 0, 0x17 },
-		Package(){0x0007FFFF, 1, 0, 0x14 },
-		Package(){0x0007FFFF, 2, 0, 0x15 },
-		Package(){0x0007FFFF, 3, 0, 0x16 },
-#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-#endif
-	})
-}
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl b/src/mainboard/lippert/frontrunner-af/acpi/sata.asl
deleted file mode 100644
index 5dd909a2c0..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/sleep.asl b/src/mainboard/lippert/frontrunner-af/acpi/sleep.asl
deleted file mode 100644
index dc6e8a4e32..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/sleep.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-
-		/* Don't allow PCIRST# to reset USB */
-		if (Arg0 == 3){
-			URRE = 0
-		}
-
-		/* Clear wake status structure. */
-		WKST [0] = 0
-		WKST [1] = 0
-	} /* End Method(\_PTS) */
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-
-		/* Re-enable HPET */
-		HPDE = 1
-
-		/* Restore PCIRST# so it resets USB */
-		if (Arg0 == 3){
-			URRE = 1
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Local1 = PWST
-		PWST = Local1
-
-		Return(WKST)
-	} /* End Method(\_WAK) */
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl b/src/mainboard/lippert/frontrunner-af/acpi/superio.asl
deleted file mode 100644
index 490d8c49d5..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/superio.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * SuperI/O devices
- */
-
-/* PS/2 Keyboard */
-Device(KBC) {
-	Name(_HID, EISAID("PNP0303"))
-	Name(_CRS, ResourceTemplate() {
-		IO(Decode16, 0x0060, 0x0060, 1, 1)
-		IO(Decode16, 0x0064, 0x0064, 1, 1)
-		IRQNoFlags(){1}
-	})
-}
-
-/* PS/2 Mouse */
-Device(PS2M) {
-	Name(_HID, EISAID("PNP0F13"))
-	Name(_CRS, ResourceTemplate() {
-		IRQNoFlags(){12}
-	})
-}
diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb_oc.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/lippert/frontrunner-af/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/lippert/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/board_info.txt
deleted file mode 100644
index 4a443cdaf0..0000000000
--- a/src/mainboard/lippert/frontrunner-af/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Category: half
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c
deleted file mode 100644
index d8d46d499e..0000000000
--- a/src/mainboard/lippert/frontrunner-af/buildOpts.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout
deleted file mode 100644
index a11e1dd0e6..0000000000
--- a/src/mainboard/lippert/frontrunner-af/cmos.layout
+++ /dev/null
@@ -1,35 +0,0 @@
-#*****************************************************************************
-# SPDX-License-Identifier: GPL-2.0-only
-
-#*****************************************************************************
-
-entries
-
-0	384	r	0	reserved_memory
-384	1	e	4	boot_option
-388	4	h	0	reboot_counter
-400	1	e	1	power_on_after_fail
-412	4	e	6	debug_level
-444	1	e	1	nmi
-728	256	h	0	user_data
-984	16	h	0	check_sum
-# Reserve the extended AMD configuration registers
-1000	24	r	0	amd_reserved
-
-enumerations
-
-#ID	value	text
-1	0	Disable
-1	1	Enable
-2	0	Enable
-2	1	Disable
-4	0	Fallback
-4	1	Normal
-6	5	Notice
-6	6	Info
-6	7	Debug
-6	8	Spew
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
deleted file mode 100644
index 5f834fc348..0000000000
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include <southbridge/amd/cimx/sb800/acpi/misc_io.asl>
-
-	#include "acpi/routing.asl"
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-
-	#include "acpi/usb_oc.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Operating System Capabilities Method */
-			Method (_OSC, 4)
-			{
-				/* Check for PCI/PCI-X/PCIe GUID */
-				If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
-				{
-					/* Let OS control everything */
-					Return (Arg3)
-				}
-				Else
-				{
-					/* Unrecognized UUID, so set bit 2 of Arg3 to 1 */
-					CreateDWordField (Arg3, 0, CDW1)
-					CDW1 |= 4
-					Return (Arg3)
-				}
-			} /* End _OSC */
-
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PICM){ Return(APR0) }   /* APIC mode */
-				Return (PR0)                  /* PIC Mode */
-			} /* end _PRT */
-
-
-
-			/* Describe the Southbridge devices */
-
-			#include <southbridge/amd/cimx/sb800/acpi/pcie.asl>
-
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			#include <southbridge/amd/cimx/sb800/acpi/usb.asl>
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			#include <southbridge/amd/cimx/sb800/acpi/audio.asl>
-
-			#include <southbridge/amd/cimx/sb800/acpi/lpc.asl>
-
-			/* PCI bridge */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			Name(CRES, ResourceTemplate() {
-				/* Set the Bus number and Secondary Bus number for the PCI0 device
-				 * The Secondary bus range for PCI0 lets the system
-				 * know what bus values are allowed on the downstream
-				 * side of this PCI bus if there is a PCI-PCI bridge.
-				 * PCI buses can have 256 secondary buses which
-				 * range from [0-0xFF] but they do not need to be
-				 * sequential.
-				 */
-				WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-					0x0000,		/* address granularity */
-					0x0000,		/* range minimum */
-					0x00FF,		/* range maximum */
-					0x0000,		/* translation */
-					0x0100,		/* length */
-					,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-				IO(Decode16, 0x004E, 0x004E, 1, 2)	/* SIO config regs */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-				IO(Decode16, 0x0E00, 0x0E00, 1, 0x80)	/* SIO runtime regs */
-#endif
-				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0000,			/* range minimum */
-					0x0CF7,			/* range maximum */
-					0x0000,			/* translation */
-					0x0CF8			/* length */
-				)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0D00,			/* range minimum */
-					0xFFFF,			/* range maximum */
-					0x0000,			/* translation */
-					0xF300			/* length */
-				)
-
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
-				/* memory space for PCI BARs below 4GB */
-				Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-			}) /* End Name(_SB.PCI0.CRES) */
-
-			Method(_CRS, 0) {
-				CreateDWordField(CRES, ^MMIO._BAS, MM1B)
-				CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				MM1B = TOM1
-				Local0 = 0x10000000 << 4
-				Local0 -= TOM1
-				MM1L = Local0
-
-				Return(CRES) /* note to change the Name buffer */
-			} /* end of Method(_SB.PCI0._CRS) */
-
-		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-}
-/* End of ASL file */
diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/lippert/frontrunner-af/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h
deleted file mode 100644
index ba6f0bb0cf..0000000000
--- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-#define USB_CONFIG		0x3F
-#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
-#define USB_CONFIG		0x0F
-#endif
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-#define PCI_CLOCK_CTRL			0x1F
-#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
-#define PCI_CLOCK_CTRL			0x1E
-#endif
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-#define AZALIA_SDIN_PIN			0x02
-#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
-#define AZALIA_SDIN_PIN			0x2A
-#endif
-
-/**
- * @def GPP_CONTROLLER
- */
-#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
-#define GPP_CONTROLLER			CIMX_OPTION_DISABLED
-#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-#endif
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			1
-
-static const CODECENTRY frontrunneraf_codec_alc886[] = /* Realtek ALC886/8 */
-{
-	/* NID, PinConfig (Verbs 71F..C) */
-	{0x11, 0x411111F0}, /* NPC */
-	{0x12, 0x411111F0}, /* DMIC */
-	{0x14, 0x01214110}, /* FRONT (Port-D) */
-	{0x15, 0x01011112}, /* SURR (Port-A) */
-	{0x16, 0x01016111}, /* CEN/LFE (Port-G) */
-	{0x17, 0x411111F0}, /* SIDESURR (Port-H) */
-	{0x18, 0x01A19930}, /* MIC1 (Port-B) */
-	{0x19, 0x411111F0}, /* MIC2 (Port-F) */
-	{0x1A, 0x0181313F}, /* LINE1 (Port-C) */
-	{0x1B, 0x411111F0}, /* LINE2 (Port-E) */
-	{0x1C, 0x411111F0}, /* CD-IN */
-	{0x1D, 0x40132601}, /* BEEP-IN */
-	{0x1E, 0x01441120}, /* S/PDIF-OUT */
-	{0x1F, 0x01C46140}, /* S/PDIF-IN */
-	{0xff, 0xffffffff} /* end of table */
-};
-
-static const CODECTBLLIST codec_tablelist[] =
-{
-	{0x10ec0888, (CODECENTRY*)&frontrunneraf_codec_alc886[0]},
-	{0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL}
-};
-
-/**
- * @def AZALIA_OEM_VERB_TABLE
- *  Mainboard specific codec verb table list
- */
-#define AZALIA_OEM_VERB_TABLE		(&codec_tablelist[0])
-
-#endif
diff --git a/src/mainboard/lippert/frontrunner-af/sema.c b/src/mainboard/lippert/frontrunner-af/sema.c
deleted file mode 100644
index b06b2cfb33..0000000000
--- a/src/mainboard/lippert/frontrunner-af/sema.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <delay.h>
-#include <OEM.h>
-
-#include <Porting.h>
-#include <AGESA.h>
-#include <northbridge/amd/agesa/dimmSpd.h>
-#include "sema.h"
-
-/* Write data block to slave on SMBUS0. */
-#define SMB0_STATUS	((SMBUS0_BASE_ADDRESS) + 0)
-#define SMB0_CONTROL	((SMBUS0_BASE_ADDRESS) + 2)
-#define SMB0_HOSTCMD	((SMBUS0_BASE_ADDRESS) + 3)
-#define SMB0_ADDRESS	((SMBUS0_BASE_ADDRESS) + 4)
-#define SMB0_DATA0	((SMBUS0_BASE_ADDRESS) + 5)
-#define SMB0_BLOCKDATA	((SMBUS0_BASE_ADDRESS) + 7)
-
-static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
-{
-	__outbyte(SMB0_STATUS, 0x1E);		// clear error status
-	__outbyte(SMB0_ADDRESS, slave & ~1);	// slave addr + direction = out
-	__outbyte(SMB0_HOSTCMD, command);	// or destination offset
-	__outbyte(SMB0_DATA0, length);		// sent before data
-	__inbyte(SMB0_CONTROL);			// reset block data array
-	while (length--)
-		__outbyte(SMB0_BLOCKDATA, *(data++));
-	__outbyte(SMB0_CONTROL, 0x54);		// execute block write, no IRQ
-
-	while (__inbyte(SMB0_STATUS) == 0x01);	// busy, no errors
-	return __inbyte(SMB0_STATUS) ^ 0x02;	// 0x02 = completed, no errors
-}
-
-#define RETRY_COUNT 100
-
-/* Use of mdelay() here would fail in romstage. */
-static void early_mdelay(int msecs)
-{
-	while (msecs--) {
-		int i;
-		for (i = 0; i < 1000; i++)
-			inb(0x80);
-	}
-}
-
-int sema_send_alive(void)
-{
-	const u8 i_am_alive[] = { 0x03 };
-	int i, j = 0;
-	char one_spd_byte;
-
-	/* Fake read just to setup SMBUS controller. */
-	if (ENV_RAMINIT)
-		smbus_readSpd(0xa0, &one_spd_byte, 1);
-
-	/* Notify the SMC we're alive and kicking, or after a while it will
-	 * effect a power cycle and switch to the alternate BIOS chip.
-	 * Should be done as late as possible. */
-
-	printk(BIOS_CRIT, "Sending BIOS alive message... ");
-
-	do {
-		i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive);
-		early_mdelay(25);
-	} while ((++j < RETRY_COUNT) && i);
-
-	if (j == RETRY_COUNT) {
-		printk(BIOS_INFO, "failed\n");
-		return -1;
-	}
-	printk(BIOS_CRIT, "took %d tries\n", j);
-
-	return 0;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/sema.h b/src/mainboard/lippert/frontrunner-af/sema.h
deleted file mode 100644
index 87b20ab282..0000000000
--- a/src/mainboard/lippert/frontrunner-af/sema.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __LIPPERT_SEMA_H__
-#define __LIPPERT_SEMA_H__
-
-/* Signal SEMA watchdog a successful boot.
- * Returns < 0 is SMBus message failed after
- * several retries.
- */
-int sema_send_alive(void);
-
-#endif
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c
deleted file mode 100644
index 393408237f..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/BiosCallOuts.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
- *
- * Dedicated reset is not needed for the on-board Intel I210 GbE controller.
- */
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	MEM_DATA_STRUCT *MemData = ConfigPtr;
-
-	printk(BIOS_INFO, "Setting DDR3 voltage: ");
-	FCH_IOMUX(184) = 2; // GPIO184: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_25: // board is not able to provide this
-		MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
-		printk(BIOS_INFO, "can't provide 1.25 V, using ");
-		__fallthrough;
-	default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
-	case VOLT1_35:
-		FCH_GPIO(184) = 0x08; // = output, disable PU, set to 0
-		printk(BIOS_INFO, "1.35 V\n");
-		break;
-	case VOLT1_5:
-		FCH_GPIO(184) = 0xC8; // = output, disable PU, set to 1
-		printk(BIOS_INFO, "1.5 V\n");
-	}
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c
deleted file mode 100644
index c1b571e713..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/OemCustomize.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeTravisDpToLvds, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt
deleted file mode 100644
index 00f3dcb22c..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: half
-Board URL: https://www.adlinktech.com/Products/PC104SBCs/PC_104_Plus_SBCs/CM2-GF
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c
deleted file mode 100644
index 4bb4c10550..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/bootblock.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb
deleted file mode 100644
index a1d15c398f..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/devicetree.cb
+++ /dev/null
@@ -1,89 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge on-board NIC
-			device pci 5.0 off end # PCIE P2P bridge
-			device pci 6.0 off end # PCIE P2P bridge
-			device pci 7.0 off end # PCIE P2P bridge
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 off end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/smsc/smscsuperio
-					device pnp 4e.0 off end		# Floppy
-					device pnp 4e.3 off end		# Parallel Port
-					device pnp 4e.4 on		# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.5 on		# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.7 on		# Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 4e.A on		# Runtime Regs
-						io 0x60 = 0x0E00
-						drq 0xF0 = 0x0B # no 32kHz
-					end
-				end # smscsuperio
-			end #LPC
-
-			device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 off end # OHCI FS/LS USB
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 off end # PCIe PortA
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 on  end # OHCI USB 10-13
-			device pci 16.2 on  end # EHCI USB 10-13
-
-			register "gpp_configuration" = "4" #1:1:1:1
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
deleted file mode 100644
index 8fa897e25e..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <arch/io.h>
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include "sema.h"
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-/* Init SIO GPIOs. */
-#define SIO_RUNTIME_BASE 0x0E00
-static const u16 sio_init_table[] = { // hi = offset, lo = value
-	0x4BA0, // GP1x: COM1/2 control   = RS232, no term, max 115200
-	0x2300, // GP10: COM1 termination = push/pull output
-	0x2400, // GP11: COM2 termination = push/pull output
-	0x2500, // GP12: COM1 RS485 mode  = push/pull output
-	0x2600, // GP13: COM2 RS485 mode  = push/pull output
-	0x2700, // GP14: COM1 speed A     = push/pull output
-	0x2900, // GP15: COM1 speed B     = push/pull output
-	0x2A00, // GP16: COM2 speed A     = push/pull output
-	0x2B00, // GP17: COM2 speed B     = push/pull output
-
-	0x3904, // GP36                   = KBDRST# function
-
-	0x4E74, // GP4x: Ethernet enable  = on
-	0x6E84, // GP44: Ethernet enable  = open drain output
-
-	// GP5x = COM2 function instead of GPIO
-	0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
-
-	0x470C, // GP60                   = WDT function
-	0x5E00, // LED2: Live LED         = off
-	0x4884, // GP61: Live LED         = LED2 function
-
-	0x5038, // GP6x: USB power        = 3x on
-	0x5580, // GP63: USB power 0/1    = open drain output
-	0x5680, // GP64: USB power 2/3    = open drain output
-	0x5780, // GP65: USB power 4/5    = open drain output
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-static void init(struct device *dev)
-{
-	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
-	int i;
-
-	/* Init Hudson GPIOs. */
-	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
-	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
-	iomux_write8(50, 2);
-	/* output set to 1 as it's never needed */
-	iomux_write8(50, 0xc0);
-	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
-	iomux_write8(197, 2);
-	/* GPIO58-56: REV_ID2-0 */
-	iomux_write8(56, 1);
-	/* inputs, disable int. pull-ups */
-	gpio_100_write8(56, 0x28);
-	iomux_write8(57, 1);
-	gpio_100_write8(57, 0x28);
-	iomux_write8(58, 1);
-	gpio_100_write8(58, 0x28);
-	/* "Gpio96": GEVENT0# signal on X2 connector (int. PU) */
-	iomux_write8(96, 1);
-	/* GPIO52,61,62,187-192 free to use on X2 connector */
-	iomux_write8(52, 1);
-	/* default to inputs with int. PU */
-	iomux_write8(61, 2);
-	iomux_write8(62, 2);
-	iomux_write8(187, 2);
-	iomux_write8(188, 2);
-	iomux_write8(189, 1);
-	iomux_write8(190, 1);
-	iomux_write8(191, 1);
-	iomux_write8(192, 1);
-	/* just in case anyone cares */
-	if (!fch_gpio_state(197))
-		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
-	printk(BIOS_INFO, "Board revision ID: %u\n",
-	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
-
-	/* Init SIO GPIOs. */
-	printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE);
-	for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
-		u16 val = sio_init_table[i];
-		outb((u8)val, SIO_RUNTIME_BASE + (val >> 8));
-	}
-
-	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
-	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
-							   0xA0) & 0xFFFFFFE0);
-	/* NormSpeed in SPI_Cntrl1 register */
-	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
-
-	/*
-	 * Notify the SMC we're alive and kicking, or after a while it will
-	 * effect a power cycle and switch to the alternate BIOS chip.
-	 * Should be done as late as possible.
-	 * Failure here does not matter if watchdog was already disabled,
-	 * by configuration or previous boot, so ignore return value.
-	 */
-	sema_send_alive();
-
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-
-	dev->ops->init = init;
-
-	/* enable GPP CLK0 */
-	/* disable GPP CLK1 thru SLT_GFX_CLK */
-	misc_write8(0, 0x0f);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c
deleted file mode 100644
index f15db2f8cb..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/BiosCallOuts.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-
-/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
- *
- * COM Express doesn't provide dedicated resets for individual lanes
- * and it's not needed for the on-board Intel I210 GbE controller.
- */
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			agesa_ReadSpd },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	MEM_DATA_STRUCT *MemData = ConfigPtr;
-
-	printk(BIOS_INFO, "Setting DDR3 voltage: ");
-	FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
-	switch (MemData->ParameterListPtr->DDR3Voltage) {
-	case VOLT1_25: // board is not able to provide this
-		MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
-		printk(BIOS_INFO, "can't provide 1.25 V, using ");
-		__fallthrough;
-	default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
-	case VOLT1_35:
-		FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
-		printk(BIOS_INFO, "1.35 V\n");
-		break;
-	case VOLT1_5:
-		FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
-		printk(BIOS_INFO, "1.5 V\n");
-	}
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c
deleted file mode 100644
index e3ffe9b39b..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/OemCustomize.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux1, Hdp1)
-	},
-	// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-	HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt
deleted file mode 100644
index 77acfae7ad..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: half
-Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132
-ROM package: SOIC8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c
deleted file mode 100644
index 5077db799b..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/bootblock.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
-
-void bootblock_mainboard_early_init(void)
-{
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb
deleted file mode 100644
index ee8b246ef1..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/devicetree.cb
+++ /dev/null
@@ -1,92 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge
-			device pci 5.0 on end # PCIE P2P bridge
-			device pci 6.0 on end # PCIE P2P bridge
-			device pci 7.0 on end # PCIE P2P bridge on-board NIC
-			device pci 8.0 off end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SM
-			device pci 14.1 off end # IDE	0x439c
-			device pci 14.2 on end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/winbond/w83627dhg
-					device pnp 4e.0 off end		# Floppy
-					device pnp 4e.1 off end		# Parallel Port
-					device pnp 4e.2 on		# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.3 on		# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.5 on		# Keyboard, Mouse
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					#device pnp 4e.6 off end	# SPI
-					device pnp 4e.307 off end	# GPIO6
-					device pnp 4e.8 off end		# WDTO, PLED
-					device pnp 4e.009 off end	# GPIO2
-					device pnp 4e.109 off end	# GPIO3
-					device pnp 4e.209 off end	# GPIO4
-					device pnp 4e.309 off end	# GPIO5
-					device pnp 4e.A off end		# ACPI
-					device pnp 4e.B off end		# HW Monitor
-				end # w83627dhg
-			end #LPC
-			device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-			device pci 14.5 off end # OHCI FS/LS USB
-			device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 on  end # PCIe PortA
-			device pci 15.1 on  end # PCIe PortB
-			device pci 15.2 on  end # PCIe PortC
-			device pci 15.3 on  end # PCIe PortD
-			device pci 16.0 off end # OHCI USB 10-13
-			device pci 16.2 off end # EHCI USB 10-13
-			register "gpp_configuration" = "4" #1:1:1:1
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
deleted file mode 100644
index 6492f56fa1..0000000000
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
-#include <southbridge/amd/cimx/sb800/gpio_oem.h>
-#include "mainboard/lippert/frontrunner-af/sema.h"
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,  /* INTA# - INTH# */
-	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,  /* Misc-nil, 0, 1, 2,  INT from Serial irq */
-	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x10, 0x11, 0x12, 0x13
-};
-
-static void init(struct device *dev)
-{
-	volatile u8 *spi_base;	/* base addr of Hudson's SPI host controller */
-
-	/* Init Hudson GPIOs. */
-	printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
-	/* GPIO50: FCH_ARST#_GATE resets stuck PCIe devices */
-	iomux_write8(50, 2);
-	/* output set to 1 as it's never needed */
-	iomux_write8(50, 0xc0);
-	/* GPIO197: BIOS_DEFAULTS# = input (int. PU) */
-	iomux_write8(197, 2);
-	/* input, disable int. pull-up */
-	gpio_100_write8(197, 0x28);
-	/* GPIO58-56: REV_ID2-0 */
-	iomux_write8(56, 1);
-	/* inputs, disable int. pull-ups */
-	gpio_100_write8(56, 0x28);
-	iomux_write8(57, 1);
-	gpio_100_write8(57, 0x28);
-	iomux_write8(58, 1);
-	gpio_100_write8(58, 0x28);
-	/* GPIO187,188,166,GPO160: GPO0-3 on COM Express connector */
-	iomux_write8(187, 2);
-	/* outputs, disable PUs, default to 0 */
-	gpio_100_write8(187, 0x08);
-	iomux_write8(188, 2);
-	gpio_100_write8(188, 0x08);
-	iomux_write8(166, 2);
-	gpio_100_write8(166, 0x08);
-	/*
-	 * needed to make GPO160 work (Hudson Register Reference
-	 * section 2.3.6.1)
-	 */
-	pm_write8(0xdc, pm_read8(0xdc) & (~0x80));
-	pm_write8(0xe6, (pm_read8(0xe6) & (~0x02)) | 1);
-	iomux_write8(160, 1);
-	gpio_100_write8(160, 0x08);
-	/* GPIO189-192: GPI0-3 on COM Express connector */
-	iomux_write8(189, 1);
-	/* default to inputs with int. PU */
-	iomux_write8(190, 1);
-	iomux_write8(191, 1);
-	iomux_write8(192, 1);
-
-	/* just in case anyone cares */
-	if (!fch_gpio_state(197))
-		printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
-	printk(BIOS_INFO, "Board revision ID: %u\n",
-	       fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
-
-	/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
-	spi_base = (u8 *)((uintptr_t)pci_read_config32(pcidev_on_root(0x14, 3),
-							   0xA0) & 0xFFFFFFE0);
-	/* NormSpeed in SPI_Cntrl1 register */
-	spi_base[0x0D] = (spi_base[0x0D] & ~0x30) | 0x20;
-
-	/*
-	 * Notify the SMC we're alive and kicking, or after a while it will
-	 * effect a power cycle and switch to the alternate BIOS chip.
-	 * Should be done as late as possible.
-	 * Failure here does not matter if watchdog was already disabled,
-	 * by configuration or previous boot, so ignore return value.
-	 */
-	sema_send_alive();
-
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-
-	dev->ops->init = init;
-
-	/* enable GPP CLK0 thru CLK1 */
-	/* disable GPP CLK2 thru SLT_GFX_CLK */
-	misc_write8(0, 0xff);
-	misc_write8(1, 0);
-	misc_write8(2, 0);
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/*
-	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
-	 * SPD read code has been made generic and moved out of the board
-	 * directory, so the ASF init is being done here.
-	 */
-	pm_write8(0x29, 0x80);
-	pm_write8(0x28, 0x61);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c
deleted file mode 100644
index aff72ca0cd..0000000000
--- a/src/mainboard/pcengines/apu1/BiosCallOuts.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <AGESA.h>
-#include <spd_bin.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <SB800.h>
-
-#include "gpio_ftns.h"
-
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_DO_RESET,			agesa_Reset },
-	{AGESA_READ_SPD,			board_ReadSpd_from_cbfs },
-	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
-	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
-	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
-	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
-	return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-
-	if (!ENV_RAMINIT)
-		return AGESA_UNSUPPORTED;
-
-	u8 index = get_spd_offset();
-
-	if (info->MemChannelId > 0)
-		return AGESA_UNSUPPORTED;
-	if (info->SocketId != 0)
-		return AGESA_UNSUPPORTED;
-	if (info->DimmId != 0)
-		return AGESA_UNSUPPORTED;
-
-	/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
-	if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
-		die("No SPD data\n");
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
deleted file mode 100644
index 46f4ddec59..0000000000
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_PCENGINES_APU1
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_AGESA_FAMILY14
-	select NORTHBRIDGE_AMD_AGESA_FAMILY14
-	select SOUTHBRIDGE_AMD_CIMX_SB800
-	select SUPERIO_NUVOTON_NCT5104D
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_CMOS_DEFAULT
-	select BOARD_ROMSIZE_KB_2048
-	select HAVE_SPD_IN_CBFS
-	select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
-	select MEMORY_MAPPED_TPM
-
-config MAINBOARD_DIR
-	default "pcengines/apu1"
-
-config MAINBOARD_PART_NUMBER
-	default "apu1"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x200000
-
-config MAX_CPUS
-	int
-	default 2
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config VGA_BIOS_ID
-	string
-	default "1002,9802"
-
-config SB800_AHCI_ROM
-	bool
-	default n
-
-choice
-	prompt "J19 pins 1-10"
-	default APU1_PINMUX_OFF_C
-
-config APU1_PINMUX_OFF_C
-	bool "disable"
-
-config APU1_PINMUX_GPIO0
-	bool "GPIO"
-
-config APU1_PINMUX_UART_C
-	bool "UART 0x3e8"
-
-endchoice
-
-config UART_C_RS485
-	bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C
-
-choice
-	prompt "J19 pins 11-20"
-	default APU1_PINMUX_OFF_D
-
-config APU1_PINMUX_OFF_D
-	bool "disable"
-
-config APU1_PINMUX_GPIO1
-	bool "GPIO"
-
-config APU1_PINMUX_UART_D
-	bool "UART 0x2e8"
-
-endchoice
-
-config UART_D_RS485
-	bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
-
-config DIMM_SPD_SIZE
-	default 128
-
-endif # BOARD_PCENGINES_APU1
diff --git a/src/mainboard/pcengines/apu1/Kconfig.name b/src/mainboard/pcengines/apu1/Kconfig.name
deleted file mode 100644
index 265f7a6bde..0000000000
--- a/src/mainboard/pcengines/apu1/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_PCENGINES_APU1
-	bool "APU1"
diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc
deleted file mode 100644
index bec5873b02..0000000000
--- a/src/mainboard/pcengines/apu1/Makefile.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_AHCI_BIOS),y)
-stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
-cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
-pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
-pci$(stripped_ahcibios_id).rom-type := optionrom
-endif
-
-bootblock-y += bootblock.c
-
-romstage-y += buildOpts.c
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-romstage-y += gpio_ftns.c
-
-ramstage-y += buildOpts.c
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-ramstage-y += gpio_ftns.c
-
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = HYNIX-H5TQ2G83CFR
-SPD_SOURCES += HYNIX-H5TQ4G83MFR
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c
deleted file mode 100644
index 254947cf8c..0000000000
--- a/src/mainboard/pcengines/apu1/OemCustomize.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <AGESA.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <PlatformMemoryConfiguration.h>
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 4)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 5)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 6)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 7)
-	},
-	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
-				HotplugDisabled,
-				PcieGen2,
-				PcieGen2,
-				AspmL0sL1, 0)
-	}
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = NULL,
-};
-
-void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
-}
-
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERRIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
- */
-static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
-
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, ONE_DIMM),
-
-	// APU soldered down memory uses memory CLK0 and CLK1 on CS0
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-
-	// APU soldered down memory requires different seeds
-#define WLSEED 0x08
-#define RXSEED 0x40
-	WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
-	HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
-
-	PSO_END
-};
-
-void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
-{
-	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
-	/* Bank interleaving is not supported on this platform */
-	InitPost->MemConfig.EnableBankIntlv = FALSE;
-}
diff --git a/src/mainboard/pcengines/apu1/OptionsIds.h b/src/mainboard/pcengines/apu1/OptionsIds.h
deleted file mode 100644
index fdd5de0cd1..0000000000
--- a/src/mainboard/pcengines/apu1/OptionsIds.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- *  This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- *    IDSOPT_IDS_ENABLED
- *    IDSOPT_ERROR_TRAP_ENABLED
- *    IDSOPT_CONTROL_ENABLED
- *    IDSOPT_TRACING_ENABLED
- *    IDSOPT_PERF_ANALYSIS
- *    IDSOPT_ASSERT_ENABLED
- *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- *
- **/
-
-#define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
-#define IDSOPT_ASSERT_ENABLED  TRUE
-
-
-#endif
diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl
deleted file mode 100644
index aa235f9f79..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/buttons.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/
- */
-
-Scope (\_SB.PCI0.SBUS)
-{
-	Device (BTNS)
-	{
-		Name (_HID, "PRP0001")
-
-		Name (_CRS, ResourceTemplate () {
-			GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionInputOnly,
-				"\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {187}
-		})
-
-		Name (_DSD, Package () {
-			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package () {
-				Package () {"compatible", Package () {"gpio-keys-polled"}},
-				Package () {"poll-interval", 100},
-				Package () {"autorepeat", 1}
-			}
-		})
-
-		Device (BTN1)
-		{
-			Name (_HID, "PRP0001")
-			Name (_DSD, Package () {
-				ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-				Package () {
-					/* BTN_1 is 0x101 in linux/input.h */
-					Package () {"linux,code", 257},
-					Package () {"linux,input-type", 1},
-					/* labeled S1 on the board, MODESW in the gpio header files */
-					Package () {"label", "switch1"},
-					Package () {"gpios", Package () {^^BTNS, 0, 0, 1 /* low-active */}},
-				}
-			})
-		}
-	}
-}
diff --git a/src/mainboard/pcengines/apu1/acpi/gpe.asl b/src/mainboard/pcengines/apu1/acpi/gpe.asl
deleted file mode 100644
index 705abf17f6..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/gpe.asl
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/pcengines/apu1/acpi/gpio.asl b/src/mainboard/pcengines/apu1/acpi/gpio.asl
deleted file mode 100644
index 20bbf60a56..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/gpio.asl
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/
- */
-
-Scope (\_SB.PCI0.SBUS)
-{
-	Device (GPIO)
-	{
-		Name (_HID, "PRP0001")
-
-		Name (_CRS, ResourceTemplate () {
-			/* ACPI_MMIO_BASE + gpio offset */
-			Memory32Fixed(ReadWrite, 0xFED80100, 0x0000100)
-		})
-
-		Name (_DSD, Package () {
-			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package () {
-				Package () {"compatible", Package () {"gpio-sb8xx"}},
-			}
-		})
-	}
-}
diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl
deleted file mode 100644
index 128e0f1f24..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/leds.asl
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Based on the example of Mika Westerberg: https://lwn.net/Articles/612062/
- */
-
-Scope (\_SB.PCI0.SBUS)
-{
-	Device (LEDS)
-	{
-		Name (_HID, "PRP0001")
-
-		Name (_CRS, ResourceTemplate () {
-			GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
-				"\\_SB.PCI0.SBUS.GPIO", 0, ResourceConsumer) {189, 190, 191}
-		})
-
-		Name (_DSD, Package () {
-			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package () {
-				Package () {"compatible", Package () {"gpio-leds"}},
-			}
-		})
-
-		Device (LED1)
-		{
-			Name (_HID, "PRP0001")
-			Name (_DSD, Package () {
-				ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-				Package () {
-					/*
-					 * From Linux Documentation/leds/leds-class.txt:
-					 * LED Device Naming
-					 * Is currently of the form:
-					 * "devicename:colour:function"
-					 */
-					Package () {"label", "apu1:green:led1"},
-					Package () {"gpios", Package () {^^LEDS, 0, 0, 1 /* low-active */}},
-					Package () {"default-state", "keep"},
-				} }) }
-
-		Device (LED2)
-		{
-			Name (_HID, "PRP0001")
-			Name (_DSD, Package () {
-				ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-				Package () {
-					Package () {"label", "apu1:green:led2"},
-					Package () {"gpios", Package () {^^LEDS, 0, 1, 1 /* low-active */}},
-					Package () {"default-state", "keep"},
-				}
-			})
-		}
-
-		Device (LED3)
-		{
-			Name (_HID, "PRP0001")
-			Name (_DSD, Package () {
-				ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-				Package () {
-					Package () {"label", "apu1:green:led3"},
-					Package () {"gpios", Package () {^^LEDS, 0, 2, 1 /* low-active */}},
-					Package () {"default-state", "keep"},
-				}
-			})
-		}
-	}
-}
diff --git a/src/mainboard/pcengines/apu1/acpi/routing.asl b/src/mainboard/pcengines/apu1/acpi/routing.asl
deleted file mode 100644
index deef1ec22c..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/routing.asl
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, INTC, 0 },
-		Package(){0x0001FFFF, 1, INTD, 0 },
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */
-		Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		Package(){0x0001FFFF, 0, 0, 18 },
-		Package(){0x0001FFFF, 1, 0, 19 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, 0, 17 },
-		Package(){0x0005FFFF, 1, 0, 18 },
-		Package(){0x0005FFFF, 2, 0, 19 },
-		Package(){0x0005FFFF, 3, 0, 16 },
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* OHCI, dev 18, 19, 22 func 0
-		 * EHCI, dev 18, 19, 22 func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-
-		/* TODO: PCIe */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
-		Package(){0x0003FFFF, 0, 0, 0x14 },
-		Package(){0x0003FFFF, 1, 0, 0x15 },
-		Package(){0x0003FFFF, 2, 0, 0x16 },
-		Package(){0x0003FFFF, 3, 0, 0x17 },
-		Package(){0x0004FFFF, 0, 0, 0x15 },
-		Package(){0x0004FFFF, 1, 0, 0x16 },
-		Package(){0x0004FFFF, 2, 0, 0x17 },
-		Package(){0x0004FFFF, 3, 0, 0x14 },
-		Package(){0x0005FFFF, 0, 0, 0x16 },
-		Package(){0x0005FFFF, 1, 0, 0x17 },
-		Package(){0x0005FFFF, 2, 0, 0x14 },
-		Package(){0x0005FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/pcengines/apu1/acpi/sata.asl b/src/mainboard/pcengines/apu1/acpi/sata.asl
deleted file mode 100644
index 6d9ff03005..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/sata.asl
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P0IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P1IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (P2IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (P3IS > 0) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (\_SB.P0IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			 \_SB.P0PR = 1
-		}
-
-		if (\_SB.P1PR) {
-			if (\_SB.P1IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P1PR = 1
-		}
-
-		if (\_SB.P2PR) {
-			if (\_SB.P2IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P2PR = 1
-		}
-
-		if (\_SB.P3PR) {
-			if (\_SB.P3IS > 0) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			\_SB.P3PR = 1
-		}
-	}
-}
diff --git a/src/mainboard/pcengines/apu1/acpi/sleep.asl b/src/mainboard/pcengines/apu1/acpi/sleep.asl
deleted file mode 100644
index 3b6fd02055..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/sleep.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Don't allow PCIRST# to reset USB */
-	if (Arg0 == 3){
-		URRE = 0
-	}
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*CSSM = 1
-	SSEN = 1*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (\_SB.SBRI <= 0x13) {
-	*	\_SB.PWDE = 0
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	WKST [0] = 0
-	WKST [1] = 0
-} /* End Method(\_PTS) */
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	HPDE = 1
-
-	/* Restore PCIRST# so it resets USB */
-	if (Arg0 == 3){
-		URRE = 1
-	}
-
-	/* Arbitrarily clear PciExpWakeStatus */
-	Local1 = PWST
-	PWST = Local1
-
-	/* if (DeRefOf(WKST [0])) {
-	*	WKST [1] = 0
-	* } else {
-	*	WKST [1] = Arg0
-	* }
-	*/
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/pcengines/apu1/acpi/superio.asl b/src/mainboard/pcengines/apu1/acpi/superio.asl
deleted file mode 100644
index d2d8a44c23..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/superio.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl b/src/mainboard/pcengines/apu1/acpi/usb_oc.asl
deleted file mode 100644
index e4ed275617..0000000000
--- a/src/mainboard/pcengines/apu1/acpi/usb_oc.asl
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-Method(UCOC, 0) {
-	Sleep(20)
-	CMTI = 0x13
-	GPSL = 0
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If (UOM0 <= 9) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if (GPB0 == PLC0) {
-				PLC0 = ~PLC0
-				\_SB.PT0D = PLC0
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (UOM1 <= 9) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (GPB1 == PLC1) {
-				PLC1 = ~PLC1
-				\_SB.PT1D = PLC1
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (UOM2 <= 9) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (GPB2 == PLC2) {
-				PLC2 = ~PLC2
-				\_SB.PT2D = PLC2
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (UOM3 <= 9) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (GPB3 == PLC3) {
-				PLC3 = ~PLC3
-				\_SB.PT3D = PLC3
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (UOM4 <= 9) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (GPB4 == PLC4) {
-				PLC4 = ~PLC4
-				\_SB.PT4D = PLC4
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (UOM5 <= 9) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (GPB5 == PLC5) {
-				PLC5 = ~PLC5
-				\_SB.PT5D = PLC5
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (UOM6 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (GPB6 == PLC6) {
-				PLC6 = ~PLC6
-				\_SB.PT6D = PLC6
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (UOM7 <= 9) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (GPB7 == PLC7) {
-				PLC7 = ~PLC7
-				\_SB.PT7D = PLC7
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (UOM8 <= 9) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (G8IS == PLC8) {
-				PLC8 = ~PLC8
-				\_SB.PT8D = PLC8
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (UOM9 <= 9) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (G9IS == 0) {
-			\_SB.PT9D = 1
-			}
-		}
-	}
-}
diff --git a/src/mainboard/pcengines/apu1/board_info.txt b/src/mainboard/pcengines/apu1/board_info.txt
deleted file mode 100644
index 68d347d93a..0000000000
--- a/src/mainboard/pcengines/apu1/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Board name: apu1
-Board URL: http://www.pcengines.ch/apu1d4.htm
-Category: half
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c
deleted file mode 100644
index 2016e7b6fa..0000000000
--- a/src/mainboard/pcengines/apu1/bootblock.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootblock_common.h>
-#include <device/pnp_type.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
-
-#define SIO_PORT 0x2e
-#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
-#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
-
-void bootblock_mainboard_early_init(void)
-{
-	if (CONFIG_UART_FOR_CONSOLE == 1)
-		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
-	else if (CONFIG_UART_FOR_CONSOLE == 0)
-		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-}
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
deleted file mode 100644
index 255893833c..0000000000
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* Select the CPU family */
-#define INSTALL_FAMILY_14_SUPPORT		TRUE
-
-/* Select the CPU socket type */
-#define INSTALL_FT1_SOCKET_SUPPORT		TRUE
-
-/* Agesa optional capabilities selection */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT		FALSE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE		FALSE
-#define BLDOPT_REMOVE_WHEA			FALSE
-#define BLDOPT_ENABLE_DMI			TRUE
-
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD	1
-
-#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_MOBILE
-#define BLDCFG_CFG_GNB_HD_AUDIO			FALSE
-#define BLDCFG_MEMORY_SODIMM_CAPABLE		TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE		FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE		UMA_NONE
-
-/* Agesa configuration values selection */
-#include <AGESA.h>
-
-/* Include the files that instantiate the configuration definitions */
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/* Instantiate all solution relevant data */
-#include <PlatformInstall.h>
diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default
deleted file mode 100644
index 06b04332a2..0000000000
--- a/src/mainboard/pcengines/apu1/cmos.default
+++ /dev/null
@@ -1,2 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout
deleted file mode 100644
index e36dd6bd61..0000000000
--- a/src/mainboard/pcengines/apu1/cmos.layout
+++ /dev/null
@@ -1,31 +0,0 @@
-entries
-
-# <start-bit> <bit-length> <config> <config-id> <parameter-name>
-0	384	r	0	reserved_memory
-384	4	r	0	reboot_bits
-# leave 3 bits to make checksummed area start byte-aligned
-392	1	e	2	boot_option
-400	4	e	4	debug_level
-# leave 7 bits to make checksummed area end byte-aligned
-408	16	h	0	check_sum
-
-enumerations
-
-#<config-id>  <value>  <label>
-## for boot_option
-2	0	Fallback
-2	1	Normal
-## for debug_level
-4	0	Emerg
-4	1	Alert
-4	2	Crit
-4	3	Err
-4	4	Warning
-4	5	Notice
-4	6	Info
-4	7	Debug
-4	8	Spew
-
-checksums
-
-checksum 392 407 408
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
deleted file mode 100644
index f8efc24242..0000000000
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ /dev/null
@@ -1,94 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-chip northbridge/amd/agesa/family14/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/agesa/family14
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x1510 inherit
-		chip northbridge/amd/agesa/family14
-			device pci 0.0 on end # Root Complex
-			device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456]
-			device pci 4.0 on end # PCIE P2P bridge on-board NIC 3
-			device pci 5.0 on end # PCIE P2P bridge on-board NIC 2
-			device pci 6.0 on end # PCIE P2P bridge on-board NIC 1
-			device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1
-			device pci 8.0 on end # NB/SB Link P2P bridge
-		end # agesa northbridge
-
-		chip southbridge/amd/cimx/sb800
-			device pci 11.0 on end # SATA
-			device pci 12.0 on end # OHCI USB 0-4
-			device pci 12.2 on end # EHCI USB 0-4
-			device pci 13.0 on end # OHCI USB 5-9
-			device pci 13.2 on end # EHCI USB 5-9
-			device pci 14.0 on end # SMBus
-			device pci 14.1 off end # IDE	0x439c
-			device pci 14.2 off end # HDA	0x4383
-			device pci 14.3 on # LPC		0x439d
-				chip superio/nuvoton/nct5104d
-					register "irq_trigger_type" = "0"
-					register "reset_gpios" = "1"
-					device pnp 2e.0 off end
-					device pnp 2e.2 on
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.10 off
-						# UART C is conditionally turned on
-						io 0x60 = 0x3e8
-						irq 0x70 = 4
-					end
-					device pnp 2e.11 off
-						# UART D is conditionally turned on
-						io 0x60 = 0x2e8
-						irq 0x70 = 3
-					end
-					device pnp 2e.008 off end
-					device pnp 2e.108 on
-						io 0x60 = 0x220
-					end
-					# GPIO0 and GPIO1 are conditionally turned on
-					device pnp 2e.007 off end
-					device pnp 2e.107 off end
-					device pnp 2e.607 off end
-					device pnp 2e.f on end
-				end
-				chip drivers/pc80/tpm
-					device pnp 0c31.0 on end
-				end # LPC TPM
-			end #LPC
-			device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
-			device pci 14.5 off end # OHCI FS/LS USB
-			#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
-			device pci 15.0 on end # PCIe PortA miniPCIe slot 2
-			device pci 15.1 off end # PCIe PortB
-			device pci 15.2 off end # PCIe PortC
-			device pci 15.3 off end # PCIe PortD
-			device pci 16.0 on end # OHCI USB 10-13
-			device pci 16.2 on end # EHCI USB 10-13
-			register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
-			register "disconnect_pcib" = "1"
-			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-		end	#southbridge/amd/cimx/sb800
-
-		chip northbridge/amd/agesa/family14
-			# These seem unnecessary
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-			device pci 18.5 on end
-			device pci 18.6 on end
-			device pci 18.7 on end
-		end # agesa northbridge
-
-	end #domain
-end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl
deleted file mode 100644
index f74bc59f45..0000000000
--- a/src/mainboard/pcengines/apu1/dsdt.asl
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* DefinitionBlock Statement */
-#include <acpi/acpi.h>
-DefinitionBlock (
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	#include <acpi/dsdt_top.asl>
-
-	#include <cpu/amd/agesa/family14/acpi/cpu.asl>
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		Device(PCI0) {
-
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
-
-		}
-	}   /* End Scope(_SB)  */
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	#include "acpi/gpe.asl"
-	#include "acpi/usb_oc.asl"
-
-	/* Contains the GPIO led and button setup for this board */
-	#include "acpi/buttons.asl"
-	#include "acpi/gpio.asl"
-	#include "acpi/leds.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
deleted file mode 100644
index 2c2eb9f7bd..0000000000
--- a/src/mainboard/pcengines/apu1/gpio_ftns.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio_legacy_gpio100.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include "gpio_ftns.h"
-
-void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting)
-{
-	u8 bdata;
-
-	iomux_write8(gpio, iomux_ftn);
-
-	bdata = gpio_100_read8(gpio);
-	bdata &= 0x07;
-	bdata |= setting; /* set direction and data value */
-	gpio_100_write8(gpio, bdata);
-}
-
-u8 read_gpio(u8 gpio)
-{
-	return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0;
-}
-
-int get_spd_offset(void)
-{
-	u8 spd_offset = read_gpio(GPIO_16);
-	return spd_offset;
-}
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h
deleted file mode 100644
index 79ed4a6d77..0000000000
--- a/src/mainboard/pcengines/apu1/gpio_ftns.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef GPIO_FTNS_H
-#define GPIO_FTNS_H
-
-#include <stdint.h>
-
-void configure_gpio(u8 gpio, u8 iomux_ftn, u8 setting);
-u8 read_gpio(u8 gpio);
-int get_spd_offset(void);
-
-#define GPIO_10         10    // PE3 Reset
-#define GPIO_11         11    // PE4 Reset
-#define GPIO_15         15    // board rev strap ms bit
-#define GPIO_16         16    // board rev strap ls bit
-#define GPIO_17         17    // TP13
-#define GPIO_18         18    // TP10
-#define GPIO_187        187   // MODESW
-#define GPIO_189        189   // LED1#
-#define GPIO_190        190   // LED2#
-#define GPIO_191        191   // LED3#
-#define GPIO_FTN_1      0x01
-#define GPIO_OUTPUT     0x08
-#define GPIO_INPUT      0x28
-#define GPIO_DATA_IN    0x80
-#define GPIO_DATA_LOW   0x00
-#define GPIO_DATA_HIGH  0x40
-
-#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu1/irq_tables.c b/src/mainboard/pcengines/apu1/irq_tables.c
deleted file mode 100644
index 06880eb107..0000000000
--- a/src/mainboard/pcengines/apu1/irq_tables.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <commonlib/bsd/helpers.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN_UP(addr, 16);
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
deleted file mode 100644
index f7b34f0c3c..0000000000
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <smbios.h>
-#include <string.h>
-#include <southbridge/amd/cimx/sb800/pci_devs.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/family14/pci_devs.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
-#include "gpio_ftns.h"
-#include <AGESA.h>
-#include <AMD.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- *
- * The PCI INTA/B/C/D pins are connected to
- * FCH pins INTE/F/G/H on the schematic so these need
- * to be routed as well.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
-	/* IDE, SATA */
-	[0x40] = 0x0B,0x0B,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x0A,0x0B,0x0A,0x0B
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
-	/* IDE, SATA */
-	[0x40] = 0x11,0x13,
-	/* GPPInt0 - 3 */
-	[0x50] = 0x10,0x11,0x12,0x13
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-/*
- * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because of PCI INT_PIN swizzle isn't implemented to match
- * the IDSEL (dev 3) of the slot, the table is adjusted for the
- * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
- * off-chip devices should get mapped to PIRQH/E/F/G.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
-	{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
-	{NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       05.0 */
-	{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       06.0 */
-	{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* miniPCIe:  07.0 */
-	{SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
-	{OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
-	{EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
-	{OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
-	{EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
-	{SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
-	{IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
-	{HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
-	{SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
-	{OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
-	{SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* miniPCIe:  15.0 */
-	{OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
-	{EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
- * once configuration file format for SPI flash storage is complete.
- */
-#define SIO_PORT 0x2e
-
-static void config_gpio_mux(void)
-{
-	struct device *uart, *gpio;
-
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
-	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
-	if (uart)
-		uart->enabled = CONFIG(APU1_PINMUX_UART_C);
-	if (gpio)
-		gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
-
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
-	gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
-	if (uart)
-		uart->enabled = CONFIG(APU1_PINMUX_UART_D);
-	if (gpio)
-		gpio->enabled = CONFIG(APU1_PINMUX_GPIO1);
-}
-
-static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
-{
-	struct resource *res;
-	res = new_resource(dev, reg);
-	res->base = val;
-	res->size = 0;
-	res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED;
-}
-
-static void config_addon_uart(void)
-{
-	struct device *uart;
-
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
-	if (uart && uart->enabled && CONFIG(UART_C_RS485))
-		pnp_raw_resource(uart, 0xf2, 0x12);
-
-	uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
-	if (uart && uart->enabled && CONFIG(UART_D_RS485))
-		pnp_raw_resource(uart, 0xf2, 0x12);
-}
-
-/**********************************************
- * Enable the dedicated functions of the board.
- **********************************************/
-#if CONFIG(GENERATE_SMBIOS_TABLES)
-static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, unsigned long *current)
-{
-	const u32 max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */
-
-	struct smbios_type16 *t = smbios_carve_table(*current, SMBIOS_PHYS_MEMORY_ARRAY,
-						     sizeof(*t), *handle);
-
-	t->use = MEMORY_ARRAY_USE_SYSTEM;
-	t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
-	t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection;
-	t->maximum_capacity = max_capacity * 1024 * 1024;
-	t->memory_error_information_handle = 0xfffe;
-	t->number_of_memory_devices = 1;
-
-	const int len = smbios_full_table_len(&t->header, t->eos);
-	*current += len;
-	return len;
-}
-
-static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, unsigned long *current)
-{
-	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
-						     sizeof(*t), *handle + 1);
-
-	t->phys_memory_array_handle = *handle;
-	t->memory_error_information_handle = 0xfffe;
-	t->total_width = agesa_dmi->T17[0][0][0].TotalWidth;
-	t->data_width = agesa_dmi->T17[0][0][0].DataWidth;
-	t->size = agesa_dmi->T17[0][0][0].MemorySize;
-	/* AGESA DMI returns form factor = 0, override it with SPD value */
-	t->form_factor = MEMORY_FORMFACTOR_SODIMM;
-	t->device_set = agesa_dmi->T17[0][0][0].DeviceSet;
-	t->device_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].DeviceLocator);
-	t->bank_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].BankLocator);
-	t->memory_type = agesa_dmi->T17[0][0][0].MemoryType;
-	t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail;
-	t->speed = agesa_dmi->T17[0][0][0].Speed;
-	t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode;
-	t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber);
-	t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber);
-	t->attributes = agesa_dmi->T17[0][0][0].Attributes;
-	t->extended_size = agesa_dmi->T17[0][0][0].ExtSize;
-	t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed;
-	t->minimum_voltage = 1500; /* From SPD: 1.5V */
-	t->maximum_voltage = 1500;
-
-	const int len = smbios_full_table_len(&t->header, t->eos);
-	*current += len;
-	return len;
-}
-
-static int mainboard_smbios_data(struct device *dev, int *handle,
-				 unsigned long *current)
-{
-	DMI_INFO *agesa_dmi;
-	int len;
-
-	agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI);
-
-	if (!agesa_dmi)
-		return 0;
-
-	len = mainboard_smbios_type16(agesa_dmi, handle, current);
-	len += mainboard_smbios_type17(agesa_dmi, handle, current);
-
-	*handle += 2;
-
-	return len;
-}
-#endif
-
-static void mainboard_enable(struct device *dev)
-{
-	/* Maintain this text unchanged for manufacture process. */
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	config_gpio_mux();
-	config_addon_uart();
-
-	/* Power off unused clock pins of GPP PCIe devices
-	 * GPP CLK0-2 are connected to the 3 ethernet chips
-	 * GPP CLK3-4 are connected to the miniPCIe slots
-	 */
-	misc_write8(0, 0x21);
-	misc_write8(1, 0x43);
-	/* GPP CLK5 is only connected to test pads -> disable */
-	misc_write8(2, 0x05);
-	/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
-	misc_write8(3, 0);
-	misc_write8(4, 0);
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-#if CONFIG(GENERATE_SMBIOS_TABLES)
-	dev->ops->get_smbios_data = mainboard_smbios_data;
-#endif
-}
-
-/*
- * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
- * into the smbios serial number location.
- */
-const char *smbios_mainboard_serial_number(void)
-{
-	static char serial[10];
-	struct device *dev;
-	uintptr_t bar18;
-	u32 mac_addr = 0;
-	int i;
-
-	/* Already initialized. */
-	if (serial[0] != 0)
-		return serial;
-
-	dev = pcidev_on_root(4, 0);
-	if (dev)
-		dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
-	if (!dev)
-		return serial;
-
-	/* Read in the last 3 bytes of NIC's MAC address. */
-	bar18 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
-	bar18 &= 0xFFFFFFF0;
-	for (i = 3; i < 6; i++) {
-		mac_addr <<= 8;
-		mac_addr |= read8((u8 *)bar18 + i);
-	}
-	mac_addr &= 0x00FFFFFF;
-	mac_addr /= 4;
-	mac_addr -= 64;
-
-	snprintf(serial, sizeof(serial), "%d", mac_addr);
-	return serial;
-}
-
-/*
- * Set up "Over Current Control 1" (reg 0x58) on the first OHCI device.
- * The remaining ports on the second device are for mcpie2/sdcard and
- * can stay at the power-on default value.
- *
- * The schematic shows this transposed mapping for the first device:
- * chipset port 0 -> port 1 (j12 external 2, usboc0#)
- * chipset port 1 -> port 4 (j17 mpcie1)
- * chipset port 2 -> port 2 (j14 header row1, usboc1#)
- * chipset port 3 -> port 3 (j14 header row2, usboc1#)
- * chipset port 4 -> port 0 (j12 external 1. usboc0#)
- *
- * Register mapping:
- * bit0-3: Mapping for HS Port 0
- * bit4-7: Mapping for HS Port 1
- * bit8-11: Mapping for HS Port 2
- * bit12-15: Mapping for HS Port 3
- * bit16-19: Mapping for HS Port 4
- * bit20-31: Reserved (0)
- *
- * power-on default: 0xfffff
- * A value >7 will disable the overcurrent detection.
- */
-static void usb_oc_setup(void)
-{
-	struct device *dev = pcidev_on_root(0x12, 0);
-
-	pci_write_config32(dev, 0x58, 0x011f0);
-}
-
-/*
- * We will stuff the memory size into the smbios sku location.
- */
-const char *smbios_system_sku(void)
-{
-	static char sku[5];
-	if (sku[0] != 0)
-		return sku;
-
-	if (!get_spd_offset())
-		snprintf(sku, sizeof(sku), "2 GB");
-	else
-		snprintf(sku, sizeof(sku), "4 GB");
-	return sku;
-}
-
-static void mainboard_final(void *chip_info)
-{
-	/* Maintain this text unchanged for manufacture process. */
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n");
-
-	/*
-	 * LED1/D7/GPIO_189 should be 0
-	 * LED2/D6/GPIO_190 should be 1
-	 * LED3/D5/GPIO_191 should be 1
-	 */
-	configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
-	configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
-	configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
-	usb_oc_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-	.final = mainboard_final,
-};
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h
deleted file mode 100644
index 44172f67d6..0000000000
--- a/src/mainboard/pcengines/apu1/platform_cfg.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _PLATFORM_CFG_H_
-#define _PLATFORM_CFG_H_
-
-/* APU has no legacy P/S2 controller */
-#define LEGACY_FREE		0 /* setting legacy free disables I/O access to 0x3F8 */
-
-/**
- * @def BIOS_SIZE
- *      BIOS_SIZE_{1,2,4,8,16}M
- *
- * In SB800, default ROM size is 1M Bytes, if your platform ROM
- * bigger than 1M you have to set the ROM size outside CIMx module and
- * before AGESA module get call.
- */
-#ifndef BIOS_SIZE
-#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
-#endif /* BIOS_SIZE */
-
-/**
- * @def SPREAD_SPECTRUM
- * @brief
- *  0 - Disable Spread Spectrum function
- *  1 - Enable  Spread Spectrum function
- */
-#define SPREAD_SPECTRUM			0
-
-/**
- * @def SB_HPET_TIMER
- * @brief
- *  0 - Disable hpet
- *  1 - Enable  hpet
- */
-#define HPET_TIMER			1
-
-/**
- * @def USB_CONFIG
- * @brief bit[0-6] used to control USB
- *   0 - Disable
- *   1 - Enable
- *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is defined at BIT0
- *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is defined at BIT1
- *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is defined at BIT2
- *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is defined at BIT3
- *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is defined at BIT4
- *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is defined at BIT5
- *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is defined at BIT6
- */
-#define USB_CONFIG		0x7F
-
-/**
- * @def PCI_CLOCK_CTRL
- * @brief bit[0-4] used for PCI Slots Clock Control,
- *   0 - disable
- *   1 - enable
- *  PCI SLOT 0 define at BIT0
- *  PCI SLOT 1 define at BIT1 -> connected to LPC devices
- *  PCI SLOT 2 define at BIT2
- *  PCI SLOT 3 define at BIT3
- *  PCI SLOT 4 define at BIT4
- */
-#define PCI_CLOCK_CTRL			0x02
-
-/**
- * @def SATA_CONTROLLER
- * @brief INCHIP Sata Controller
- */
-#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
-
-/**
- * @def SATA_MODE
- * @brief INCHIP Sata Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_MODE			CONFIG_SB800_SATA_MODE
-
-/**
- * @brief INCHIP Sata IDE Controller Mode
- */
-#define IDE_LEGACY_MODE			0
-#define IDE_NATIVE_MODE			1
-
-/**
- * @def SATA_IDE_MODE
- * @brief INCHIP Sata IDE Controller Mode
- *   NOTE: DO NOT ALLOW SATA & IDE use same mode
- */
-#define SATA_IDE_MODE			IDE_LEGACY_MODE
-
-/**
- * @def EXTERNAL_CLOCK
- * @brief 00/10: Reference clock from crystal oscillator via
- *  PAD_XTALI and PAD_XTALO
- *
- * @def INTERNAL_CLOCK
- * @brief 01/11: Reference clock from internal clock through
- *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
- */
-#define EXTERNAL_CLOCK		0x00
-#define INTERNAL_CLOCK		0x01
-
-/* NOTE: inagua have to using internal clock,
- * otherwise can not detect sata drive
- */
-#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
-
-/**
- * @def SATA_PORT_MULT_CAP_RESERVED
- * @brief 1 ON, 0 0FF
- */
-#define SATA_PORT_MULT_CAP_RESERVED	1
-
-/**
- * @def   AZALIA_AUTO
- * @brief Detect Azalia controller automatically.
- *
- * @def   AZALIA_DISABLE
- * @brief Disable Azalia controller.
-
- * @def   AZALIA_ENABLE
- * @brief Enable Azalia controller.
- */
-#define AZALIA_AUTO			0
-#define AZALIA_DISABLE			1
-#define AZALIA_ENABLE			2
-
-/**
- * @brief INCHIP HDA controller
- */
-#define AZALIA_CONTROLLER		AZALIA_AUTO
-
-/**
- * @def AZALIA_PIN_CONFIG
- * @brief
- *  0 - disable
- *  1 - enable
- */
-#define AZALIA_PIN_CONFIG		1
-
-/**
- * @def AZALIA_SDIN_PIN
- * @brief
- *  SDIN0 is defined at BIT0 & BIT1
- *   00 - GPIO PIN
- *   01 - Reserved
- *   10 - As a Azalia SDIN pin
- *  SDIN1 is defined at BIT2 & BIT3
- *  SDIN2 is defined at BIT4 & BIT5
- *  SDIN3 is defined at BIT6 & BIT7
- */
-//#define AZALIA_SDIN_PIN		0xAA
-#define AZALIA_SDIN_PIN			0x2A
-
-/**
- * @def GPP_CONTROLLER
- */
-#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
-
-/**
- * @def GPP_CFGMODE
- * @brief GPP Link Configuration
- * four possible configuration:
- *  GPP_CFGMODE_X4000
- *  GPP_CFGMODE_X2200
- *  GPP_CFGMODE_X2110
- *  GPP_CFGMODE_X1111
- */
-#define GPP_CFGMODE			GPP_CFGMODE_X1111
-
-/**
- * @def NB_SB_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define NB_SB_GEN2			TRUE
-
-/**
- * @def SB_GPP_GEN2
- *    0  - Disable
- *    1  - Enable
- */
-#define SB_GPP_GEN2			TRUE
-
-/**
- * @def SB_GPP_UNHIDE_PORTS
- *    TRUE   - ports visible always, even port empty
- *    FALSE  - ports invisible if port empty
- */
-#define SB_GPP_UNHIDE_PORTS		FALSE
-
-/**
- * @def   GEC_CONFIG
- *    0  - Enable
- *    1  - Disable
- */
-#define GEC_CONFIG			0
-
-/**
- * @def USB_RX_MODE
- *    0x00 - leave Cg2Pll voltage at default value (1.222V)
- *    0x01 - lower Cg2Pll voltage to 1.1V
- *
- * Workaround for reset issues via outb(0x6, 0xcf9).
- * For details check:
- * AMD SB800 Family Product Errata,
- * Section 15. USB Resets Asynchronously With Port CF9h Hard Reset
- *
- */
-
-#define USB_RX_MODE 0x00
-
-#endif /* _PLATFORM_CFG_H_ */
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
deleted file mode 100644
index f5948274fb..0000000000
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <amdblocks/acpimmio.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include "gpio_ftns.h"
-#include <SB800.h>
-#include <sb_cimx.h>
-
-static void early_lpc_init(void)
-{
-	/* PC Engines requires system boot when power is applied. This feature is
-	 * controlled in PM_REG 5Bh register. "Always Power On" works by writing a
-	 * value of 05h.
-	 */
-	u8 bdata = pm_read8(SB_PMIOA_REG5B);
-	bdata &= 0xf8; //clear bits 0-2
-	bdata |= 0x05; //set bits 0,2
-	pm_write8(SB_PMIOA_REG5B, bdata);
-
-	/* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
-	bdata = pm_read8(SB_PMIOA_REGEA);
-	bdata &= 0xfe; //clear bit 0
-	bdata |= 0x01; //set bit 0
-	pm_write8(SB_PMIOA_REGEA, bdata);
-
-	//configure required GPIOs
-	configure_gpio(GPIO_10,  GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
-	configure_gpio(GPIO_11,  GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
-	configure_gpio(GPIO_15,  GPIO_FTN_1, GPIO_INPUT);
-	configure_gpio(GPIO_16,  GPIO_FTN_1, GPIO_INPUT);
-	configure_gpio(GPIO_17,  GPIO_FTN_1, GPIO_INPUT);
-	configure_gpio(GPIO_18,  GPIO_FTN_1, GPIO_INPUT);
-	configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT);
-	configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
-	configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
-	configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
-}
-
-void board_BeforeAgesa(struct sysinfo *cb)
-{
-	early_lpc_init();
-}
diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex
deleted file mode 100644
index 72377c4257..0000000000
--- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ2G83CFR.spd.hex
+++ /dev/null
@@ -1,234 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# HYNIX-H5TQ2G83CFR
-
-# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
-#  0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-#    bits[3:0]: 1 = 128 SPD Bytes Used
-#    bits[6:4]: 1 = 256 SPD Bytes Total
-#    bit7     : 0 = CRC covers bytes 0 ~ 125
-11
-
-#  1 SPD Revision -
-#    0x10 = Revision 1.0
-10
-#  2 Key Byte / DRAM Device Type
-#    bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-#  3 Key Byte / Module Type
-#    bits[3:0]: 3 = SO-DIMM
-#    bits[7:4]:     reserved
-03
-
-#  4 SDRAM CHIP Density and Banks
-#    bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-#    bits[6:4]: 0 = 3 (8 banks)
-#    bit7     :     reserved
-03
-
-#  5 SDRAM Addressing
-#    bits[2:0]: 1 = 10 Column Address Bits
-#    bits[5:3]: 3 = 15 Row Address Bits
-#    bits[7:6]:     reserved
-19
-
-#  6 Module Nominal Voltage, VDD
-#    bit0     : 0 = 1.5 V operable
-#    bit1     : 0 = NOT 1.35 V operable
-#    bit2     : 0 = NOT 1.25 V operable
-#    bits[7:3]:     reserved
-00
-
-#  7 Module Organization
-#    bits[2:0]: 1 = 8 bits
-#    bits[5:3]: 0 = 1 Rank
-#    bits[7:6]:     reserved
-01
-
-#  8 Module Memory Bus Width
-#    bits[2:0]: 3 = Primary bus width is 64 bits
-#    bits[4:3]: 0 = 0 bits (no bus width extension)
-#    bits[7:5]:     reserved
-03
-
-#  9 Fine Timebase (FTB) Dividend / Divisor
-#    bits[3:0]: 0x01 divisor
-#    bits[7:4]: 0x01 dividend
-#               1 / 1 = 1.0 ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-#    1 / 8 = .125 ns
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-#    0x0c  = tCKmin of 1.5 ns = in multiples of MTB
-0C
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-#    Cas Latencies of 11 - 5 are supported
-7E 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-#    0x6C = 13.5ns - DDR3-1333
-6C
-
-# 17 Minimum Write Recovery Time (tWRmin)
-#    0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-#    0x6E = 13.5ns -  DDR3-1333
-6C
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-#   0x30 = 6ns
-30
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-#    0x6C = 13.5ns -  DDR3-1333
-6C
-
-# 21 Upper Nibbles for tRAS and tRC
-#    bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-#    bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-#    0x120 = 36ns - DDR3-1333 (see byte 21)
-20
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-#    0x28C = 49.5ns - DDR3-1333
-8C
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-#    0x500 = 160ns - for 2 Gigabit chips
-00 05
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-#    0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-#    0x3c =  7.5ns -  All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-#    0x00F0 = 30ns -  DDR3-1333, 1 KB page size
-00 F0
-
-# 30 SDRAM Optional Feature
-#    bit0     : 1= RZQ/6 supported
-#    bit1     : 1 = RZQ/7 supported
-#    bits[6:2]:     reserved
-#    bit7     : 1 = DLL Off mode supported
-83
-
-# 31 SDRAM Thermal and Refresh Options
-#    bit0     : 1 = Temp up to 95c supported
-#    bit1     : 0 = 85-95c uses 2x refresh rate
-#    bit2     : 1 = Auto Self Refresh supported
-#    bit3     : 0 = no on die thermal sensor
-#    bits[6:4]:     reserved
-#    bit7     : 0 = partial self refresh supported
-05
-
-# 32 Module Thermal Sensor
-#    0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-#    bits[1:0]: 2 = Signal Loading
-#    bits[3:2]:     reserved
-#    bits[6:4]: 4 = Die count
-#    bit7     : 0 = Standard Monolithic DRAM Device
-42
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-#      39 (reserved)
-00
-
-#      40 - 47 (reserved)
-00 00 00 00 00 00 00 00
-
-#      48 - 55 (reserved)
-00 00 00 00 00 00 00 00
-
-#      56 - 59 (reserved)
-00 00 00 00
-
-#      60 Raw Card Extension, Module Nominal Height
-#              bits[4:0]: 0 = <= 15mm tall
-#              bits[7:5]: 0 = raw card revision 0-3
-00
-
-#      61 Module Maximum Thickness
-#              bits[3:0]: 0 = thickness front <= 1mm
-#              bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-#      62 Reference Raw Card Used
-#              bits[4:0]: 0 = Reference Raw card A used
-#              bits[6:5]: 0 = revision 0
-#              bit7 : 0 = Reference raw cards A through AL
-00
-
-#      63 Address Mapping from Edge Connector to DRAM
-#              bit0 : 0 = standard mapping (not mirrored)
-#              bits[7:1]: reserved
-00
-
-#      64 - 71 (reserved)
-00 00 00 00 00 00 00 00
-
-#      72 - 79 (reserved)
-00 00 00 00 00 00 00 00
-
-#      80 - 87 (reserved)
-00 00 00 00 00 00 00 00
-
-#      88 - 95 (reserved)
-00 00 00 00 00 00 00 00
-
-#      96 - 103 (reserved)
-00 00 00 00 00 00 00 00
-
-#      104 - 111 (reserved)
-00 00 00 00 00 00 00 00
-
-#      112 - 116 (reserved)
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-#           0x0001 = AMD
-00 01
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-00
-
-# 120 Module ID: Module Manufacture Year in BCD
-#     0x13 = 2013
-# 121 Module ID: Module Manufacture week
-#     0x12 = 12th week
-13 12
-
-#      122 - 125: Module Serial Number
-00 00 00 00
-
-#      126 - 127: Cyclical Redundancy Code
-c4 1b
diff --git a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex
deleted file mode 100644
index b6d24b48a1..0000000000
--- a/src/mainboard/pcengines/apu1/spd/HYNIX-H5TQ4G83MFR.spd.hex
+++ /dev/null
@@ -1,237 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# HYNIX-H5TQ4G83MFR
-
-# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
-#  0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-#    bits[3:0]: 1 = 128 SPD Bytes Used
-#    bits[6:4]: 1 = 256 SPD Bytes Total
-#    bit7     : 0 = CRC covers bytes 0 ~ 125
-11
-
-#  1 SPD Revision -
-#    0x10 = Revision 1.0
-10
-#  2 Key Byte / DRAM Device Type
-#    bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-#  3 Key Byte / Module Type
-#    bits[3:0]: 3 = SO-DIMM
-#    bits[7:4]:     reserved
-03
-
-#  4 SDRAM CHIP Density and Banks
-#    bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-#    bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-#    bits[6:4]: 0 = 3 (8 banks)
-#    bit7     :     reserved
-04
-
-#  5 SDRAM Addressing
-#    bits[2:0]: 1 = 10 Column Address Bits
-#    bits[5:3]: 3 = 15 Row Address Bits
-#    bits[5:3]: 4 = 16 Row Address Bits
-#    bits[7:6]:     reserved
-21
-
-#  6 Module Nominal Voltage, VDD
-#    bit0     : 0 = 1.5 V operable
-#    bit1     : 0 = NOT 1.35 V operable
-#    bit2     : 0 = NOT 1.25 V operable
-#    bits[7:3]:     reserved
-00
-
-#  7 Module Organization
-#    bits[2:0]: 1 = 8 bits
-#    bits[5:3]: 0 = 1 Rank
-#    bits[7:6]:     reserved
-01
-
-#  8 Module Memory Bus Width
-#    bits[2:0]: 3 = Primary bus width is 64 bits
-#    bits[4:3]: 0 = 0 bits (no bus width extension)
-#    bits[7:5]:     reserved
-03
-
-#  9 Fine Timebase (FTB) Dividend / Divisor
-#    bits[3:0]: 0x01 divisor
-#    bits[7:4]: 0x01 dividend
-#               1 / 1 = 1.0 ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-#    1 / 8 = .125 ns
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-#    0x0c  = tCKmin of 1.5 ns = in multiples of MTB
-0C
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-#    Cas Latencies of 11 - 5 are supported
-7E 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-#    0x6C = 13.5ns - DDR3-1333
-6C
-
-# 17 Minimum Write Recovery Time (tWRmin)
-#    0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-#    0x6E = 13.5ns -  DDR3-1333
-6C
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-#   0x30 = 6ns
-30
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-#    0x6C = 13.5ns -  DDR3-1333
-6C
-
-# 21 Upper Nibbles for tRAS and tRC
-#    bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-#    bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-#    0x120 = 36ns - DDR3-1333 (see byte 21)
-20
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-#    0x28C = 49.5ns - DDR3-1333
-8C
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-#    0x500 = 160ns - for 2 Gigabit chips
-#    0x820 = 260ns - for 4 Gigabit chips
-20 08
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-#    0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-#    0x3c =  7.5ns -  All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-#    0x00F0 = 30ns -  DDR3-1333, 1 KB page size
-00 F0
-
-# 30 SDRAM Optional Feature
-#    bit0     : 1= RZQ/6 supported
-#    bit1     : 1 = RZQ/7 supported
-#    bits[6:2]:     reserved
-#    bit7     : 1 = DLL Off mode supported
-83
-
-# 31 SDRAM Thermal and Refresh Options
-#    bit0     : 1 = Temp up to 95c supported
-#    bit1     : 0 = 85-95c uses 2x refresh rate
-#    bit2     : 1 = Auto Self Refresh supported
-#    bit3     : 0 = no on die thermal sensor
-#    bits[6:4]:     reserved
-#    bit7     : 0 = partial self refresh supported
-05
-
-# 32 Module Thermal Sensor
-#    0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-#    bits[1:0]: 2 = Signal Loading
-#    bits[3:2]:     reserved
-#    bits[6:4]: 4 = Die count
-#    bit7     : 0 = Standard Monolithic DRAM Device
-42
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-#      39 (reserved)
-00
-
-#      40 - 47 (reserved)
-00 00 00 00 00 00 00 00
-
-#      48 - 55 (reserved)
-00 00 00 00 00 00 00 00
-
-#      56 - 59 (reserved)
-00 00 00 00
-
-#      60 Raw Card Extension, Module Nominal Height
-#              bits[4:0]: 0 = <= 15mm tall
-#              bits[7:5]: 0 = raw card revision 0-3
-00
-
-#      61 Module Maximum Thickness
-#              bits[3:0]: 0 = thickness front <= 1mm
-#              bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-#      62 Reference Raw Card Used
-#              bits[4:0]: 0 = Reference Raw card A used
-#              bits[6:5]: 0 = revision 0
-#              bit7 : 0 = Reference raw cards A through AL
-00
-
-#      63 Address Mapping from Edge Connector to DRAM
-#              bit0 : 0 = standard mapping (not mirrored)
-#              bits[7:1]: reserved
-00
-
-#      64 - 71 (reserved)
-00 00 00 00 00 00 00 00
-
-#      72 - 79 (reserved)
-00 00 00 00 00 00 00 00
-
-#      80 - 87 (reserved)
-00 00 00 00 00 00 00 00
-
-#      88 - 95 (reserved)
-00 00 00 00 00 00 00 00
-
-#      96 - 103 (reserved)
-00 00 00 00 00 00 00 00
-
-#      104 - 111 (reserved)
-00 00 00 00 00 00 00 00
-
-#      112 - 116 (reserved)
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-#           0x0001 = AMD
-00 01
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-00
-
-# 120 Module ID: Module Manufacture Year in BCD
-#     0x13 = 2013
-# 121 Module ID: Module Manufacture week
-#     0x12 = 12th week
-13 12
-
-#      122 - 125: Module Serial Number
-00 00 00 00
-
-#      126 - 127: Cyclical Redundancy Code
-7b 97