Remove VIA CN700 northbridge support

Change-Id: I6c33d35718cc445ce67fc625d71420ded3828d8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

10 files changed, 0 insertions, 1263 deletions

diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig
deleted file mode 100644
index 1619ff15a3..0000000000
--- a/src/northbridge/via/cn700/Kconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-config NORTHBRIDGE_VIA_CN700
-	bool
-	select NO_MMCONF_SUPPORT
-	select HAVE_DEBUG_RAM_SETUP
-	select LATE_CBMEM_INIT
-
-# TODO: Values are from the CX700 datasheet, not sure if this matches CN700.
-# TODO: What should be the per-chipset default value here?
-choice
-	prompt "Onboard graphics"
-	default CN700_VIDEO_MB_32MB
-	depends on NORTHBRIDGE_VIA_CN700
-
-# TODO: Disabling onboard graphics is not yet supported in the code.
-config CN700_VIDEO_MB_OFF
-	bool "Disabled, 0KB"
-config CN700_VIDEO_MB_8MB
-	bool "Enabled, 8MB"
-config CN700_VIDEO_MB_16MB
-	bool "Enabled, 16MB"
-config CN700_VIDEO_MB_32MB
-	bool "Enabled, 32MB"
-config CN700_VIDEO_MB_64MB
-	bool "Enabled, 64MB"
-config CN700_VIDEO_MB_128MB
-	bool "Enabled, 128MB"
-
-endchoice
-
-if NORTHBRIDGE_VIA_CN700
-
-config VIDEO_MB
-	int
-	default 0   if CN700_VIDEO_MB_OFF
-	default 8   if CN700_VIDEO_MB_8MB
-	default 16  if CN700_VIDEO_MB_16MB
-	default 32  if CN700_VIDEO_MB_32MB
-	default 64  if CN700_VIDEO_MB_64MB
-	default 128 if CN700_VIDEO_MB_128MB
-
-config VGA_BIOS_ID
-	string
-	depends on VGA_BIOS
-	default "1106,3344"
-
-endif
diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc
deleted file mode 100644
index f7f288f732..0000000000
--- a/src/northbridge/via/cn700/Makefile.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y)
-
-ramstage-y += northbridge.c
-ramstage-y += agp.c
-ramstage-y += vga.c
-romstage-y += raminit.c
-
-endif
diff --git a/src/northbridge/via/cn700/acpi/hostbridge.asl b/src/northbridge/via/cn700/acpi/hostbridge.asl
deleted file mode 100644
index 2fb41588bb..0000000000
--- a/src/northbridge/via/cn700/acpi/hostbridge.asl
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-
-Name (_HID, EisaId ("PNP0A03"))
-Name (_UID, 1)
-Name (_ADR, 0x00000000)
-Name (_BBN, 0)
-
-/* The DRAM controller */
-Device (MEMC)
-{
-	Name (_ADR, 0x00000003)
-
-	OperationRegion (MEMB, PCI_Config, 0x00, 0xEF)
-	Field (MEMB, DWordAcc, NoLock, Preserve) {
-
-		/* DRAM Rank Ending Address */
-		Offset (0x40),
-		R0EA, 8,	/* Rank 0 Ending Address */
-		R1EA, 8,	/* Rank 1 Ending Address */
-		R2EA, 8,	/* Rank 2 Ending Address */
-		R3EA, 8,	/* Rank 3 Ending Address */
-	}
-
-	/* Find the top of DRAM */
-	Method (TOLM, 0) {
-		/* Find the last occupied rank's end. */
-		Store (R3EA, Local0)
-		If (LEqual (Local0, Zero)) {
-			Store (R2EA, Local0)
-		}
-		If (LEqual (Local0, Zero)) {
-			Store (R1EA, Local0)
-		}
-		If (LEqual (Local0, Zero)) {
-			Store (R0EA, Local0)
-		}
-		/* The granularity is 64M */
-		ShiftLeft (Local0, 26, Local0)
-		Return (Local0)
-	}
-}
-
-Name (XCRS, ResourceTemplate () {
-	/* All PCI busses */
-	WordBusNumber (ResourceConsumer, MinNotFixed, MaxNotFixed, PosDecode,
-		0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
-
-	/* IO-space, sans the PCI regs. */
-	WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8,
-		,,, TypeStatic)
-	WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300,
-		,,, TypeStatic)
-
-	/* The space from top of DRAM to IOAPIC */
-	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-		/* This is a template that gets filled in _CRS() */
-		0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,,
-		MEM0, AddressRangeMemory, TypeStatic)
-})
-Method (_CRS, 0) {
-
-	/* MEM0 is from the top of RAM to IOAPIC */
-	CreateDWordField (XCRS, \_SB.PCI0.MEM0._MIN, MEML)
-	CreateDWordField (XCRS, \_SB.PCI0.MEM0._MAX, MEMH)
-	CreateDWordField (XCRS, \_SB.PCI0.MEM0._LEN, LENM)
-	Store (\_SB.PCI0.MEMC.TOLM, MEML)
-	Subtract (IO_APIC_ADDR, 1, MEMH)
-	Subtract (IO_APIC_ADDR, MEML, LENM)
-
-	Return (XCRS);
-}
diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c
deleted file mode 100644
index d0355730f5..0000000000
--- a/src/northbridge/via/cn700/agp.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "northbridge.h"
-#include "cn700.h"
-
-/* This is the main AGP device, and only one used when configured for AGP 2.0 */
-static void agp_init(struct device *dev)
-{
-	u32 reg32;
-
-	/* Some of this may not be necessary (should be handled by the OS). */
-	printk(BIOS_DEBUG, "Enabling AGP.\n");
-
-	/* Allow R/W access to AGP registers. */
-	pci_write_config8(dev, 0x4d, 0x15);
-
-	/* Setup PCI latency timer. */
-	pci_write_config8(dev, 0xd, 0x8);
-
-	/*
-	 * Set to AGP 3.0 Mode, which should theoretically render the rest of
-	 * the registers set here pointless.
-	 */
-	pci_write_config8(dev, 0x84, 0xb);
-
-	/* AGP Request Queue Size */
-	pci_write_config8(dev, 0x4a, 0x1f);
-
-	/*
-	 * AGP Hardware Support (default 0xc4)
-	 * 7: AGP SBA Enable (1 to Enable)
-	 * 6: AGP Enable
-	 * 5: Reserved
-	 * 4: Fast Write Enable
-	 * 3: AGP8X Mode Enable
-	 * 2: AGP4X Mode Enable
-	 * 1: AGP2X Mode Enable
-	 * 0: AGP1X Mode Enable
-	 */
-	pci_write_config8(dev, 0x4b, 0xc4);
-
-	/* Enable AGP Backdoor */
-	pci_write_config8(dev, 0xb5, 0x03);
-
-	/* Set aperture to 32 MB. */
-	/* TODO: Use config option, explain how it works. */
-	pci_write_config32(dev, 0x94, 0x00010f38);
-	/* Set GART Table Base Address (31:12). */
-	pci_write_config32(dev, 0x98, (0x1558 << 12));
-	/* Set AGP Aperture Base. */
-	pci_write_config32(dev, 0x10, 0xf8000008);
-
-	/* Enable CPU/PMSTR GART Access. */
-	reg32 = pci_read_config8(dev, 0xbf);
-	reg32 |= 0x80;
-	pci_write_config8(dev, 0xbf, reg32);
-
-	/* Enable AGP Aperture. */
-	reg32 = pci_read_config32(dev, 0x94);
-	reg32 |= (3 << 7);
-	pci_write_config32(dev, 0x90, reg32);
-
-	/* AGP Control */
-	pci_write_config8(dev, 0xbc, 0x21);
-	pci_write_config8(dev, 0xbd, 0xd2);
-
-	/*
-	 * AGP Pad, driving strength, and delay control. All this should be
-	 * constant, seeing as the VGA controller is onboard.
-	 */
-	pci_write_config8(dev, 0x40, 0xc7);
-	pci_write_config8(dev, 0x41, 0xdb);
-	pci_write_config8(dev, 0x42, 0x10);
-	pci_write_config8(dev, 0x43, 0xdb);
-	pci_write_config8(dev, 0x44, 0x24);
-
-	/* AGPC CKG Control */
-	pci_write_config8(dev, 0xc0, 0x02);
-	pci_write_config8(dev, 0xc1, 0x02);
-}
-
-static const struct device_operations agp_operations = {
-	.read_resources   = DEVICE_NOOP,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = agp_init,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver agp_driver __pci_driver = {
-	.ops    = &agp_operations,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_CN700_AGP,
-};
-
-/*
- * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
- * config in this device takes presidence. We configure both just to be safe.
- */
-static void agp_bridge_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Setting up AGP bridge device\n");
-
-	pci_write_config16(dev, 0x4, 0x0007);
-
-	/* Secondary Bus Number */
-	pci_write_config8(dev, 0x19, 0x01);
-	/* Subordinate Bus Number */
-	pci_write_config8(dev, 0x1a, 0x01);
-	/* I/O Base */
-	pci_write_config8(dev, 0x1c, 0xd0);
-	/* I/O Limit */
-	pci_write_config8(dev, 0x1d, 0xd0);
-
-	/* Memory Base */
-	pci_write_config16(dev, 0x20, 0xfb00);
-	/* Memory Limit */
-	pci_write_config16(dev, 0x22, 0xfcf0);
-	/* Prefetchable Memory Base */
-	pci_write_config16(dev, 0x24, 0xf400);
-	/* Prefetchable Memory Limit */
-	pci_write_config16(dev, 0x26, 0xf7f0);
-	/* Enable VGA Compatible Memory/IO Range */
-	pci_write_config8(dev, 0x3e, 0x08);
-
-	/* Second PCI Bus Control (see datasheet) */
-	pci_write_config8(dev, 0x40, 0x83);
-	pci_write_config8(dev, 0x41, 0x43);
-	pci_write_config8(dev, 0x42, 0xe2);
-	pci_write_config8(dev, 0x43, 0x44);
-	pci_write_config8(dev, 0x44, 0x34);
-	pci_write_config8(dev, 0x45, 0x72);
-}
-
-static void agp_bridge_read_resources(struct device *dev)
-{
-	struct resource *resource;
-
-	resource = new_resource(dev, 0);
-	if (resource) {
-		resource->base	= 0;
-		resource->size	= 0;
-		resource->limit = 0xffffUL;
-		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
-	}
-
-	resource = new_resource(dev, 1);
-	if (resource) {
-		resource->base = 0;
-		resource->size = 0;
-		resource->limit = 0xfffffffffULL;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		resource->flags |= IORESOURCE_BRIDGE;
-	}
-
-	resource = new_resource(dev, 2);
-	if (resource) {
-		resource->base = 0;
-		resource->size = 0;
-		resource->limit = 0xffffffffULL;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-	}
-}
-
-static const struct device_operations agp_bridge_operations = {
-	.read_resources   = agp_bridge_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = agp_bridge_init,
-	.scan_bus         = pci_scan_bridge,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver agp_bridge_driver __pci_driver = {
-	.ops    = &agp_bridge_operations,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_CN700_BRIDGE,
-};
diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h
deleted file mode 100644
index a5e8c1cf10..0000000000
--- a/src/northbridge/via/cn700/cn700.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __VIA_CN700_H__
-#define __VIA_CN700_H__
-
-/* VGA stuff */
-#define SR_INDEX		0x3c4
-#define SR_DATA			0x3c5
-#define CRTM_INDEX		0x3b4
-#define CRTM_DATA		0x3b5
-#define CRTC_INDEX		0x3d4
-#define CRTC_DATA		0x3d5
-
-/* Memory controller registers */
-#define RANK0_END		0x40
-#define RANK1_END		0x41
-#define RANK2_END		0x42
-#define RANK3_END		0x43
-#define RANK0_START		0x48
-#define RANK1_START		0x49
-#define RANK2_START		0x4a
-#define RANK3_START		0x4b
-#define DDR_PAGE_CTL		0x69
-#define DRAM_REFRESH_COUNTER	0x6a
-#define DRAM_MISC_CTL		0x6b
-#define CH_A_DQS_OUTPUT_DELAY	0x70
-#define CH_A_MD_OUTPUT_DELAY	0x71
-
-/* RAM init commands */
-#define RAM_COMMAND_NORMAL	0x0
-#define RAM_COMMAND_NOP		0x1
-#define RAM_COMMAND_PRECHARGE	0x2
-#define RAM_COMMAND_MRS		0x3
-#define RAM_COMMAND_CBR		0x4
-
-#endif
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
deleted file mode 100644
index 78bb6f95d1..0000000000
--- a/src/northbridge/via/cn700/northbridge.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <lib.h>
-#include <cbmem.h>
-#include <cpu/cpu.h>
-#include "northbridge.h"
-#include "cn700.h"
-
-static void memctrl_init(struct device *dev)
-{
-	struct device *vlink_dev;
-	u16 reg16;
-	u8 ranks, pagec, paged, pagee, pagef, shadowreg;
-
-	/* Set up the VGA framebuffer size. */
-	reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
-	pci_write_config16(dev, 0xa0, reg16);
-
-	/* Set up VGA timers. */
-	pci_write_config8(dev, 0xa2, 0x44);
-
-	for (ranks = 0x4b; ranks >= 0x48; ranks--) {
-		if (pci_read_config8(dev, ranks)) {
-			ranks -= 0x48;
-			break;
-		}
-	}
-	if (ranks == 0x47)
-		ranks = 0x00;
-	reg16 = 0xaae0;
-	reg16 |= ranks;
-	/* GMINT Misc. FrameBuffer rank */
-	pci_write_config16(dev, 0xb0, reg16);
-	/* AGPCINT Misc. */
-	pci_write_config8(dev, 0xb8, 0x08);
-
-	/* Shadow RAM */
-	pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
-	/* PAGE C, D, E are all read write enable */
-	pci_write_config8(dev, 0x80, pagec);
-	pci_write_config8(dev, 0x81, paged);
-	pci_write_config8(dev, 0x82, pagee);
-	/* PAGE F are read/writable */
-	shadowreg = pci_read_config8(dev, 0x83);
-	shadowreg |= pagef;
-	pci_write_config8(dev, 0x83, shadowreg);
-	/* vlink mirror */
-	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
-				    PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
-	if (vlink_dev) {
-		pci_write_config8(vlink_dev, 0x61, pagec);
-		pci_write_config8(vlink_dev, 0x62, paged);
-		pci_write_config8(vlink_dev, 0x64, pagee);
-
-		shadowreg = pci_read_config8(vlink_dev, 0x63);
-		shadowreg |= pagef;
-		pci_write_config8(vlink_dev, 0x63, shadowreg);
-	}
-}
-
-static const struct device_operations memctrl_operations = {
-	.read_resources = DEVICE_NOOP,
-	.init           = memctrl_init,
-};
-
-static const struct pci_driver memctrl_driver __pci_driver = {
-	.ops    = &memctrl_operations,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
-};
-
-static void pci_domain_set_resources(struct device *dev)
-{
-	/* The order is important to find the correct RAM size. */
-	static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
-	struct device *mc_dev;
-	u32 pci_tolm;
-
-	printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
-
-	pci_tolm = find_pci_tolm(dev->link_list);
-	mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
-				 PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
-
-	if (mc_dev) {
-		unsigned long tomk, tolmk;
-		unsigned char rambits;
-		int i, idx;
-
-		/*
-		 * Once the register value is not zero, the RAM size is
-		 * this register's value multiply 64 * 1024 * 1024.
-		 */
-		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
-			rambits = pci_read_config8(mc_dev, ramregs[i]);
-			if (rambits != 0)
-				break;
-		}
-
-		tomk = rambits * 64 * 1024;
-		printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
-		/* Compute the Top Of Low Memory (TOLM), in Kb. */
-		tolmk = pci_tolm >> 10;
-		if (tolmk >= tomk) {
-			/* The PCI hole does does not overlap the memory. */
-			tolmk = tomk;
-		}
-
-		set_late_cbmem_top((tolmk - CONFIG_VIDEO_MB * 1024) * 1024);
-
-		/* Report the memory regions. */
-		idx = 10;
-		/* TODO: Hole needed? */
-		ram_resource(dev, idx++, 0, 640);	/* First 640k */
-		/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
-		ram_resource(dev, idx++, 768,
-			     (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
-	}
-	assign_resources(dev->link_list);
-}
-
-static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
-	.enable_resources = NULL,
-	.init             = NULL,
-	.scan_bus         = pci_domain_scan_bus,
-};
-
-static void cpu_bus_init(struct device *dev)
-{
-	initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
-	.read_resources   = DEVICE_NOOP,
-	.set_resources    = DEVICE_NOOP,
-	.enable_resources = DEVICE_NOOP,
-	.init             = cpu_bus_init,
-	.scan_bus         = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
-	printk(BIOS_SPEW, "In cn700 enable_dev for device %s.\n", dev_path(dev));
-
-	/* Set the operations if it is a special bus type. */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		dev->ops = &cpu_bus_ops;
-	}
-}
-
-struct chip_operations northbridge_via_cn700_ops = {
-	CHIP_NAME("VIA CN700 Northbridge")
-	.enable_dev = enable_dev,
-};
diff --git a/src/northbridge/via/cn700/northbridge.h b/src/northbridge/via/cn700/northbridge.h
deleted file mode 100644
index 1780b4d664..0000000000
--- a/src/northbridge/via/cn700/northbridge.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_VIA_CN700_H
-#define NORTHBRIDGE_VIA_CN700_H
-
-extern unsigned int cn700_scan_root_bus(struct device *root, unsigned int max);
-
-#endif /* NORTHBRIDGE_VIA_CN700_H */
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
deleted file mode 100644
index e8a7a17814..0000000000
--- a/src/northbridge/via/cn700/raminit.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <northbridge/via/cn700/raminit.h>
-#include <console/console.h>
-#include <spd.h>
-#include <delay.h>
-#include "cn700.h"
-
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
-#define PRINT_DEBUG_MEM(x)		printk(BIOS_DEBUG, x)
-#define PRINT_DEBUG_MEM_HEX8(x)		printk(BIOS_DEBUG, "%02x", x)
-#define PRINT_DEBUG_MEM_HEX16(x)	printk(BIOS_DEBUG, "%04x", x)
-#define PRINT_DEBUG_MEM_HEX32(x)	printk(BIOS_DEBUG, "%08x", x)
-#define DUMPNORTH()			dump_pci_device(PCI_DEV(0, 0, 0))
-#else
-#define PRINT_DEBUG_MEM(x)
-#define PRINT_DEBUG_MEM_HEX8(x)
-#define PRINT_DEBUG_MEM_HEX16(x)
-#define PRINT_DEBUG_MEM_HEX32(x)
-#define DUMPNORTH()
-#endif
-
-static void do_ram_command(pci_devfn_t dev, u8 command)
-{
-	u8 reg;
-
-	/* TODO: Support for multiple DIMMs. */
-
-	reg = pci_read_config8(dev, DRAM_MISC_CTL);
-	reg &= 0xf8;		/* Clear bits 2-0. */
-	reg |= command;
-	pci_write_config8(dev, DRAM_MISC_CTL, reg);
-}
-
-static void c7_pci_write_config8(pci_devfn_t dev, u8 reg, u8 val)
-{
-	udelay(200);
-	pci_write_config8(dev, reg, val);
-}
-
-/**
- * Configure the bus between the CPU and the northbridge. This might be able to
- * be moved to post-ram code in the future. For the most part, these registers
- * should not be messed around with. These are too complex to explain short of
- * copying the datasheets into the comments, but most of these values are from
- * the BIOS Porting Guide, so they should work on any board. If they don't,
- * try the values from your factory BIOS.
- *
- * TODO: Changing the DRAM frequency doesn't work (hard lockup).
- *
- * @param dev The northbridge's CPU Host Interface (D0F2).
- */
-static void c7_cpu_setup(pci_devfn_t dev)
-{
-	/* Host bus interface registers (D0F2 0x50-0x67) */
-	/* Request phase control */
-	c7_pci_write_config8(dev, 0x50, 0x88);
-	/* CPU Interface Control */
-	c7_pci_write_config8(dev, 0x51, 0x7a);
-	c7_pci_write_config8(dev, 0x52, 0x6f);
-	/* Arbitration */
-	c7_pci_write_config8(dev, 0x53, 0x88);
-	/* Miscellaneous Control */
-	c7_pci_write_config8(dev, 0x54, 0x1e);
-	c7_pci_write_config8(dev, 0x55, 0x16);
-	/* Write Policy */
-	c7_pci_write_config8(dev, 0x56, 0x01);
-	/* Miscellaneous Control */
-	/*
-	 * DRAM Operating Frequency (bits 7:5)
-	 *      000 : 100MHz    001 : 133MHz
-	 *      010 : 166MHz    011 : 200MHz
-	 *      100 : 266MHz    101 : 333MHz
-	 *      110/111 : Reserved
-	 */
-	/* CPU Miscellaneous Control */
-	c7_pci_write_config8(dev, 0x59, 0x44);
-
-	/* Write Policy */
-	c7_pci_write_config8(dev, 0x5d, 0xb2);
-	/* Bandwidth Timer */
-	c7_pci_write_config8(dev, 0x5e, 0x88);
-	/* CPU Miscellaneous Control */
-	c7_pci_write_config8(dev, 0x5f, 0xc7);
-
-	/* Line DRDY# Timing Control */
-	c7_pci_write_config8(dev, 0x60, 0xff);
-	c7_pci_write_config8(dev, 0x61, 0xff);
-	c7_pci_write_config8(dev, 0x62, 0x0f);
-	/* QW DRDY# Timing Control */
-	c7_pci_write_config8(dev, 0x63, 0xff);
-	c7_pci_write_config8(dev, 0x64, 0xff);
-	c7_pci_write_config8(dev, 0x65, 0x0f);
-	/* Read Line Burst DRDY# Timing Control */
-	c7_pci_write_config8(dev, 0x66, 0xff);
-	c7_pci_write_config8(dev, 0x67, 0x30);
-
-	/* Host Bus I/O Circuit (see datasheet) */
-	/* Host Address Pullup/down Driving */
-	c7_pci_write_config8(dev, 0x70, 0x11);
-	c7_pci_write_config8(dev, 0x71, 0x11);
-	c7_pci_write_config8(dev, 0x72, 0x11);
-	c7_pci_write_config8(dev, 0x73, 0x11);
-	/* Miscellaneous Control */
-	c7_pci_write_config8(dev, 0x74, 0x35);
-	/* AGTL+ I/O Circuit */
-	c7_pci_write_config8(dev, 0x75, 0x28);
-	/* AGTL+ Compensation Status */
-	c7_pci_write_config8(dev, 0x76, 0x74);
-	/* AGTL+ Auto Compensation Offest */
-	c7_pci_write_config8(dev, 0x77, 0x00);
-	/* Host FSB CKG Control */
-	c7_pci_write_config8(dev, 0x78, 0x0a);
-	/* Address/Address Clock Output Delay Control */
-	c7_pci_write_config8(dev, 0x79, 0xaa);
-	/* Address Strobe Input Delay Control */
-	c7_pci_write_config8(dev, 0x7a, 0x24);
-	/* Address CKG Rising/Falling Time Control */
-	c7_pci_write_config8(dev, 0x7b, 0xaa);
-	/* Address CKG Clock Rising/Falling Time Control */
-	c7_pci_write_config8(dev, 0x7c, 0x00);
-	/* Undefined (can't remember why I did this) */
-	c7_pci_write_config8(dev, 0x7d, 0x6d);
-	c7_pci_write_config8(dev, 0x7e, 0x00);
-	c7_pci_write_config8(dev, 0x7f, 0x00);
-	c7_pci_write_config8(dev, 0x80, 0x1b);
-	c7_pci_write_config8(dev, 0x81, 0x0a);
-	c7_pci_write_config8(dev, 0x82, 0x0a);
-	c7_pci_write_config8(dev, 0x83, 0x0a);
-}
-
-/**
- * Set up DRAM size according to SPD data. Eventually, DRAM timings should be
- * done in a similar manner.
- *
- * @param ctrl The northbridge devices and SPD addresses.
- */
-static void sdram_set_size(const struct mem_controller *ctrl)
-{
-	u8 density, ranks, result, col;
-
-	ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS);
-	ranks = (ranks & 0x07) + 1;
-	density = spd_read_byte(ctrl->channel0[0],
-				SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
-	switch (density) {
-	case 0x80:
-		result = 0x08;	/* 512MB / 64MB = 0x08 */
-		break;
-	case 0x40:
-		result = 0x04;
-		break;
-	case 0x20:
-		result = 0x02;
-		break;
-	case 0x10:
-		result = 0xff;	/* 16GB */
-		break;
-	case 0x08:
-		result = 0xff;	/* 8GB */
-		break;
-	case 0x04:
-		result = 0xff;	/* 4GB */
-		break;
-	case 0x02:
-		result = 0x20;	/* 2GB */
-		break;
-	case 0x01:
-		result = 0x10;	/* 1GB */
-		break;
-	default:
-		result = 0;
-	}
-
-	switch (result) {
-	case 0xff:
-		die("DRAM module size too big, not supported by CN700\n");
-		break;
-	case 0:
-		die("DRAM module has unknown density\n");
-		break;
-	default:
-		printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);
-	}
-
-	pci_write_config8(ctrl->d0f3, 0x40, result);
-	pci_write_config8(ctrl->d0f3, 0x48, 0x00);
-	if (ranks == 2) {
-		pci_write_config8(ctrl->d0f3, 0x41, result * ranks);
-		pci_write_config8(ctrl->d0f3, 0x49, result);
-	}
-	/* Size mirror */
-	pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2);
-	pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2);
-	/* Low Top Address */
-	pci_write_config8(ctrl->d0f3, 0x84, 0x00);
-	pci_write_config8(ctrl->d0f3, 0x85, (result * ranks) << 2);
-	pci_write_config8(ctrl->d0f3, 0x88, (result * ranks) << 2);
-
-	/* Physical-Virtual Mapping */
-	if (ranks == 2)
-		pci_write_config8(ctrl->d0f3, 0x54,
-				  1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
-	if (ranks == 1)
-		pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4);
-	pci_write_config8(ctrl->d0f3, 0x55, 0x00);
-	/* Virtual rank interleave, disable */
-	pci_write_config32(ctrl->d0f3, 0x58, 0x00);
-
-	/* MA Map Type */
-	result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
-	if (result == 8) {
-		col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
-		switch (col) {
-		case 10:
-			pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
-			break;
-		case 11:
-			pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
-			break;
-		case 12:
-			pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
-			break;
-		}
-	} else if (result == 4) {
-		col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
-		switch (col) {
-		case 9:
-			pci_write_config8(ctrl->d0f3, 0x50, 0x00);
-			break;
-		case 10:
-			pci_write_config8(ctrl->d0f3, 0x50, 0x20);
-			break;
-		case 11:
-			pci_write_config8(ctrl->d0f3, 0x50, 0x40);
-			break;
-		case 12:
-			pci_write_config8(ctrl->d0f3, 0x50, 0x60);
-			break;
-		}
-	}
-	pci_write_config8(ctrl->d0f3, 0x51, 0x00);
-}
-
-/**
- * Set up various RAM and other control registers statically. Some of these may
- * not be needed, other should be done with SPD info, but that's a project for
- * the future.
- */
-static void sdram_set_registers(const struct mem_controller *ctrl)
-{
-	u8 reg;
-
-	/* Set WR = 5 */
-	pci_write_config8(ctrl->d0f3, 0x61, 0xe0);
-	/* Set CAS = 4 */
-	pci_write_config8(ctrl->d0f3, 0x62, 0xfa);
-	/* DRAM timing-3 */
-	pci_write_config8(ctrl->d0f3, 0x63, 0xca);
-	/* DRAM timing-4 */
-	pci_write_config8(ctrl->d0f3, 0x64, 0xcc);
-	/* DIMM command / Address Selection */
-	pci_write_config8(ctrl->d0f3, 0x67, 0x00);
-	/* Disable cross bank/multi page mode */
-	pci_write_config8(ctrl->d0f3, 0x69, 0x00);
-	/* Disable refresh now */
-	pci_write_config8(ctrl->d0f3, 0x6a, 0x00);
-
-	/* Frequency 100 MHz */
-	pci_write_config8(ctrl->d0f3, 0x90, 0x00);
-	pci_write_config8(ctrl->d0f2, 0x57, 0x18);
-	/* Allow manual DLL reset */
-	pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
-
-	/* Bank/Rank Interleave Address Select */
-	pci_write_config8(ctrl->d0f3, 0x52, 0x33);
-	pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
-
-	/* Set to DDR2 SDRAM, BL = 8 (0xc8, 0xc0 for bl = 4) */
-	pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
-
-	/* DRAM Bus Turn-Around Setting */
-	pci_write_config8(ctrl->d0f3, 0x60, 0x03);
-	/* DRAM Arbitration Control */
-	pci_write_config8(ctrl->d0f3, 0x66, 0x80);
-	/*
-	 * DQS Tuning: testing on a couple different boards has shown this is
-	 * static, or close enough that it can be. Which is good, because the
-	 * tuning function used too many registers.
-	 */
-	/* DQS Output Delay for Channel A */
-	pci_write_config8(ctrl->d0f3, 0x70, 0x00);
-	/* MD Output Delay for Channel A */
-	pci_write_config8(ctrl->d0f3, 0x71, 0x01);
-	pci_write_config8(ctrl->d0f3, 0x73, 0x01);
-
-	/* DRAM arbitration timer */
-	pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
-
-	/* DRAM signal timing control */
-	pci_write_config8(ctrl->d0f3, 0x74, 0x01);
-	pci_write_config8(ctrl->d0f3, 0x75, 0x01);
-	pci_write_config8(ctrl->d0f3, 0x76, 0x06);
-	pci_write_config8(ctrl->d0f3, 0x77, 0x92);
-	pci_write_config8(ctrl->d0f3, 0x78, 0x83);
-	pci_write_config8(ctrl->d0f3, 0x79, 0x83);
-	pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
-	pci_write_config8(ctrl->d0f3, 0x7b, 0x10);
-
-	/* DRAM clocking control */
-	pci_write_config8(ctrl->d0f3, 0x91, 0x01);
-	/* CS/CKE Clock Phase Control */
-	pci_write_config8(ctrl->d0f3, 0x92, 0x02);
-	/* SCMD/MA Clock Phase Control */
-	pci_write_config8(ctrl->d0f3, 0x93, 0x02);
-	/* DCLKO Feedback Mode Output Control */
-	pci_write_config8(ctrl->d0f3, 0x94, 0x00);
-	pci_write_config8(ctrl->d0f3, 0x9d, 0x0f);
-
-	/* SDRAM ODT Control */
-	pci_write_config8(ctrl->d0f3, 0xda, 0x80);
-	/* Channel A DQ/DQS CKG Output Delay Control */
-	pci_write_config8(ctrl->d0f3, 0xdc, 0x54);
-	/* Channel A DQ/DQS CKG Output Delay Control */
-	pci_write_config8(ctrl->d0f3, 0xdd, 0x55);
-	/* ODT lookup table */
-	pci_write_config8(ctrl->d0f3, 0xd8, 0x01);
-	pci_write_config8(ctrl->d0f3, 0xd9, 0x0a);
-
-	/* DDR SDRAM control */
-	pci_write_config8(ctrl->d0f3, 0x6d, 0xc0);
-	pci_write_config8(ctrl->d0f3, 0x6f, 0x41);
-
-	/* DQ/DQS Strength Control */
-	pci_write_config8(ctrl->d0f3, 0xd0, 0xaa);
-
-	/* Compensation Control */
-	pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /* Enable autocompensation */
-	/* ODT (some are set with driving select above) */
-	pci_write_config8(ctrl->d0f3, 0xd4, 0x80);
-	pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
-	/* Memory Pads Driving and Range Select */
-	pci_write_config8(ctrl->d0f3, 0xd6, 0xaa);
-
-	pci_write_config8(ctrl->d0f3, 0xe0, 0xee);
-	pci_write_config8(ctrl->d0f3, 0xe2, 0xac);
-	pci_write_config8(ctrl->d0f3, 0xe4, 0x66);
-	pci_write_config8(ctrl->d0f3, 0xe6, 0x33);
-	pci_write_config8(ctrl->d0f3, 0xe8, 0x86);
-	/* DQS / DQ CKG Duty Cycle Control */
-	pci_write_config8(ctrl->d0f3, 0xec, 0x00);
-	/* MCLK Output Duty Control */
-	pci_write_config8(ctrl->d0f3, 0xee, 0x00);
-	/* DQS CKG Input Delay Control */
-	pci_write_config8(ctrl->d0f3, 0xef, 0x10);
-
-	/* DRAM duty control */
-	pci_write_config8(ctrl->d0f3, 0xed, 0x10);
-
-	/* SMM and APIC decoding, we do not use SMM */
-	reg = 0x29;
-	pci_write_config8(ctrl->d0f3, 0x86, reg);
-	/* SMM and APIC decoding mirror */
-	pci_write_config8(ctrl->d0f7, 0xe6, reg);
-
-	/* DRAM module configuration */
-	pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
-}
-
-static void sdram_set_post(const struct mem_controller *ctrl)
-{
-	pci_devfn_t dev = ctrl->d0f3;
-
-	/* Enable multipage mode. */
-	pci_write_config8(dev, 0x69, 0x03);
-
-	/* Enable refresh. */
-	pci_write_config8(dev, 0x6a, 0x32);
-
-	/* VGA device. */
-	pci_write_config16(dev, 0xa0, (1 << 15));
-	pci_write_config16(dev, 0xa4, 0x0010);
-}
-
-static void sdram_enable(pci_devfn_t dev, u8 *rank_address)
-{
-	u8 i;
-
-	/* 1. Apply NOP. */
-	PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
-	do_ram_command(dev, RAM_COMMAND_NOP);
-	udelay(100);
-	read32(rank_address + 0x10);
-
-	/* 2. Precharge all. */
-	udelay(400);
-	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
-	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
-	read32(rank_address + 0x10);
-
-	/* 3. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
-	do_ram_command(dev, RAM_COMMAND_MRS);
-	read32(rank_address + 0x120000);	/* EMRS DLL Enable */
-	read32(rank_address + 0x800);	/* MRS DLL Reset */
-
-	/* 4. Precharge all again. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
-	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
-	read32(rank_address + 0x0);
-
-	/* 5. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
-	do_ram_command(dev, RAM_COMMAND_CBR);
-	for (i = 0; i < 8; i++) {
-		read32(rank_address + 0x20);
-		udelay(100);
-	}
-
-	/* 6. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n");
-	/* Safe value for now, BL = 8, WR = 5, CAS = 4 */
-	/*
-	 * (E)MRS values are from the BPG. No direct explanation is given, but
-	 * they should somehow conform to the JEDEC DDR2 SDRAM Specification
-	 * (JESD79-2C).
-	 */
-	do_ram_command(dev, RAM_COMMAND_MRS);
-	read32(rank_address + 0x002258); /* MRS command */
-	read32(rank_address + 0x121c20); /* EMRS OCD Default */
-	read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
-
-	/* 8. Normal operation */
-	PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
-	do_ram_command(dev, RAM_COMMAND_NORMAL);
-	read32(rank_address + 0x30);
-}
-
-/*
- * Support one DIMM with up to 2 ranks.
- */
-void ddr_ram_setup(const struct mem_controller *ctrl)
-{
-	u8 reg;
-
-	c7_cpu_setup(ctrl->d0f2);
-	sdram_set_registers(ctrl);
-	sdram_set_size(ctrl);
-	sdram_enable(ctrl->d0f3, (u8 *)0);
-	reg = pci_read_config8(ctrl->d0f3, 0x41);
-	if (reg != 0)
-		sdram_enable(ctrl->d0f3,
-			     (u8 *)(pci_read_config8(ctrl->d0f3, 0x40) << 26));
-	sdram_set_post(ctrl);
-}
diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h
deleted file mode 100644
index d78ad1fd0c..0000000000
--- a/src/northbridge/via/cn700/raminit.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-#define DIMM_SOCKETS 1		/* Only one works, for now. */
-
-struct mem_controller {
-	pci_devfn_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
-	u8 channel0[DIMM_SOCKETS];
-};
-
-void ddr_ram_setup(const struct mem_controller *ctrl);
-
-/* mainboard specific */
-int spd_read_byte(unsigned device, unsigned address);
-void main(unsigned long bist);
-
-#endif
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
deleted file mode 100644
index 493159abe6..0000000000
--- a/src/northbridge/via/cn700/vga.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Note: Some of the VGA control registers are located on the memory
- * controller. Registers are set both in raminit.c and northbridge.c.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <arch/interrupt.h>
-#include "northbridge.h"
-#include "cn700.h"
-#include <x86emu/regs.h>
-
-static int via_cn700_int15_handler(void)
-{
-	int res = 0;
-	printk(BIOS_DEBUG, "via_cn700_int15_handler\n");
-	switch(X86_EAX & 0xffff) {
-	case 0x5f19:
-		break;
-	case 0x5f18:
-		X86_EAX = 0x5f;
-		X86_EBX = 0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
-		X86_ECX = 0x060;
-		res = 1;
-		break;
-	case 0x5f00:
-		X86_EAX = 0x8600;
-		break;
-	case 0x5f01:
-		X86_EAX = 0x5f;
-		X86_ECX = (X86_ECX & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
-		res = 1;
-		break;
-	case 0x5f02:
-		X86_EAX = 0x5f;
-		X86_EBX = (X86_EBX & 0xffff0000) | 2;
-		X86_ECX = (X86_ECX & 0xffff0000) | 0x401;  // PAL + crt only
-		X86_EDX = (X86_EDX & 0xffff0000) | 0;  // TV Layout - default
-		res = 1;
-		break;
-	case 0x5f0f:
-		X86_EAX = 0x860f;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				X86_EAX & 0xffff);
-		break;
-	}
-	return res;
-}
-
-static void vga_init(struct device *dev)
-{
-	u8 reg8;
-
-	mainboard_interrupt_handlers(0x15, &via_cn700_int15_handler);
-
-#undef OLD_BOCHS_METHOD
-#ifdef OLD_BOCHS_METHOD
-	printk(BIOS_DEBUG, "Copying BOCHS BIOS to 0xf000\n");
-	/*
-	 * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
-	 * This is for compatibility with the VGA ROM's BIOS callbacks.
-	 */
-	memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
-#endif
-
-	/* Set memory rate to 200 MHz. */
-	outb(0x3d, CRTM_INDEX);
-	reg8 = inb(CRTM_DATA);
-	reg8 &= 0x0f;
-	reg8 |= (0x1 << 4);
-	outb(0x3d, CRTM_INDEX);
-	outb(reg8, CRTM_DATA);
-
-	/* Set framebuffer size. */
-	reg8 = (CONFIG_VIDEO_MB / 4);
-	outb(0x39, SR_INDEX);
-	outb(reg8, SR_DATA);
-
-	pci_write_config8(dev, 0x04, 0x07);
-	pci_write_config8(dev, 0x0d, 0x20);
-	pci_write_config32(dev, 0x10, 0xf4000008);
-	pci_write_config32(dev, 0x14, 0xfb000000);
-
-	printk(BIOS_DEBUG, "Initializing VGA...\n");
-
-	pci_dev_init(dev);
-
-	/* It's not clear if these need to be programmed before or after
-	 * the VGA BIOS runs. Try both, clean up later. */
-	/* Set memory rate to 200 MHz (again). */
-	outb(0x3d, CRTM_INDEX);
-	reg8 = inb(CRTM_DATA);
-	reg8 &= 0x0f;
-	reg8 |= (0x1 << 4);
-	outb(0x3d, CRTM_INDEX);
-	outb(reg8, CRTM_DATA);
-
-	/* Set framebuffer size (again). */
-	reg8 = (CONFIG_VIDEO_MB / 4);
-	outb(0x39, SR_INDEX);
-	outb(reg8, SR_DATA);
-
-#ifdef OLD_BOCHS_METHOD
-	/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
-	memset((void *)0xf0000, 0, 0x10000);
-#endif
-}
-
-static const struct device_operations vga_operations = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = vga_init,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
-	.ops    = &vga_operations,
-	.vendor = PCI_VENDOR_ID_VIA,
-	.device = PCI_DEVICE_ID_VIA_CN700_VGA,
-};