diff options
| author | Wisley Chen <wisley.chen@quantatw.com> | 2020-10-31 01:24:43 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-20 16:34:35 +0000 |
| commit | e928391f74aa75fb92a701a8586c4b9050f2a964 (patch) | |
| tree | 2485d8bd366c62372f06119da0d05fc7e55710fa | |
| parent | bb1ada6d3a2866a6839ad2d44763184bc893f72f (diff) | |
mb/google/volteer/var/elemi: enable Genesys Logic GL9763E
Enable Genesys GL9763E as PCI-to-eMMC bridge.
BUG=b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I858c12151df5b6fc19132869317edfa1b090335d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/volteer/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/elemi/overridetree.cb | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 07a5fde7a1..1553a3af54 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENERIC_MAX98357A + select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 4afc795afd..d4c40f9795 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -6,6 +6,13 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Enable EMMC PCIE 5 using clk 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -184,6 +191,7 @@ chip soc/intel/tigerlake device generic 0 on end end end + device ref pcie_rp5 on end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. |