diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-09-11 18:51:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-22 07:02:26 +0000 |
| commit | ccbe5307d80c28953132a02dae97f0a984ffecbc (patch) | |
| tree | 5c2f35626031ccb0f92a670ab2f49a17a6cb60f0 | |
| parent | e5655a11d21cd0b51220b11a58014c1855864075 (diff) | |
soc/intel/jasperlake: Enable processor thermal control using PCI_DEVFN
Enable processor thermal control using PCI dev path function instead of
Device4Enable parameter in devicetree. This change removes the dependency
on Device4Enable in devicetree. We can enable and disable this thermal
control using on and off support with PCI device entry in devicetree.
BRANCH=None
BUG=None
TEST=Built and tested on dedede board
Change-Id: I0463236996ad001af506c9966840b27fe44d60d2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
4 files changed, 3 insertions, 8 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index c23717eabc..1f72eb1432 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,9 +155,6 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - # Enable processor thermal control - register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C # chipset_lockdown configuration diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 035ccbd301..f8fea47aa5 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -128,9 +128,6 @@ chip soc/intel/jasperlake # Enable DPTF register "dptf_enable" = "1" - # Enable Processor Thermal Control - register "Device4Enable" = "1" - # Add PL1 and PL2 values register "power_limits_config" = "{ .tdp_pl1_override = 6, diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3f0b910327..6b5f599911 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -142,7 +142,6 @@ struct soc_intel_jasperlake_config { uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; - uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index ff9bfbfe72..cdd088eb26 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -183,7 +183,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) if (params->ScsSdCardEnabled) params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; - params->Device4Enable = config->Device4Enable; + /* Enable Processor Thermal Control */ + dev = pcidev_path_on_root(SA_DEVFN_DPTF); + params->Device4Enable = is_dev_enabled(dev); /* Set TccActivationOffset */ params->TccActivationOffset = config->tcc_offset; |