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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-23 00:18:08 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:16:17 +0000 |
| commit | cc975c5c65c27f13c00dc7eabec02386002a2c53 (patch) | |
| tree | 76d675734dce3a4b34fb86285873fa6258e0c39e | |
| parent | f09221c033a27d87f39ab074ee53a109a861f096 (diff) | |
soc/amd/cezanne/Kconfig: select missing SSE2 option
This will set the corresponding enable bit in CR4 in bootblock_crt0.S
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 08d8397bf6..9b766736f0 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -28,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART + select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS |