diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-11-02 09:10:30 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:33:32 +0100 |
| commit | b9ea8b3fb0082840b0c9d449535f4c49c2e885ac (patch) | |
| tree | 32df5c3cf78aca3c9f737312c8a60998a1498f62 | |
| parent | 9aa031e47157e37e8f3cd80cbc80215e2843eaa9 (diff) | |
lynxpoint: PMIR register rename
The register that controls global reset is named the Power
Mangement Initialization Regiser (PMIR). Update the defines
to reflect the documentation.
Additionally, there is no core well reset control according to the
EDS. There is, however, a CF9 lock field to lock this register down.
Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_me.c | 11 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 6 |
2 files changed, 7 insertions, 10 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 1eb30a1ff7..e41b801a8b 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -112,18 +112,15 @@ int intel_early_me_uma_size(void) static inline void set_global_reset(int enable) { - u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); - - /* Clear CF9 Without Resume Well Reset Enable */ - etr3 &= ~ETR3_CWORWRE; + u32 pmir = pci_read_config32(PCH_LPC_DEV, PMIR); /* CF9GR indicates a Global Reset */ if (enable) - etr3 |= ETR3_CF9GR; + pmir |= PMIR_CF9GR; else - etr3 &= ~ETR3_CF9GR; + pmir &= ~PMIR_CF9GR; - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + pci_write_config32(PCH_LPC_DEV, PMIR, pmir); } int intel_early_me_init_done(u8 status) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 3738a13dbd..e1d9db4378 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -129,9 +129,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 -#define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define PMIR 0xac +#define PMIR_CF9LOCK (1 << 31) +#define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) |