diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-25 21:37:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-31 10:35:42 +0000 |
| commit | af1cbe2278b4ca3252d48ba36814db940e9d4237 (patch) | |
| tree | a342792a4d174736967049441822729c2e2954be | |
| parent | 9a100b5c1df00b4b4570f914412068e3d86343f4 (diff) | |
cpu/x86: make set_msr_bit publicly available
Haswell and model_2065 implement a static set_msr_bit helper which
should be publicly available instead. Move it to cpu/x86.
Change-Id: I68b314c917f15fc6e5351de1c539d5a3ae646df8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36338
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/cpu/intel/haswell/finalize.c | 19 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/finalize.c | 17 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 17 | ||||
| -rw-r--r-- | src/include/cpu/x86/msr.h | 20 |
4 files changed, 20 insertions, 53 deletions
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index b75d145ffd..b838f3476d 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -22,25 +22,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -#if 0 -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} -#endif - void intel_cpu_haswell_finalize_smm(void) { #if 0 diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 3c1c2db1c4..a0a3fe227b 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -23,23 +23,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index c9d53769b3..d51fb21847 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -23,23 +23,6 @@ * Document Number 504790 * Revision 1.6.0, June 2012 */ -static void msr_set_bit(unsigned int reg, unsigned int bit) -{ - msr_t msr = rdmsr(reg); - - if (bit < 32) { - if (msr.lo & (1 << bit)) - return; - msr.lo |= 1 << bit; - } else { - if (msr.hi & (1 << (bit - 32))) - return; - msr.hi |= 1 << (bit - 32); - } - - wrmsr(reg, msr); -} - void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 8c558ce8ac..2710e7f1fc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -301,5 +301,25 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg) return MCA_ERRTYPE_UNKNOWN; } + +/* Helper for setting single MSR bits */ +static inline void msr_set_bit(unsigned int reg, unsigned int bit) +{ + msr_t msr = rdmsr(reg); + + if (bit < 32) { + if (msr.lo & (1 << bit)) + return; + msr.lo |= 1 << bit; + } else { + if (msr.hi & (1 << (bit - 32))) + return; + msr.hi |= 1 << (bit - 32); + } + + wrmsr(reg, msr); +} + + #endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ |