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authorJeremy Compostella <jeremy.compostella@intel.com>2023-10-30 20:43:50 -0700
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-11-02 13:31:33 +0000
commit8bde652241ecb8356540b3a418012d3c7e570ac3 (patch)
tree4dfd2469fca03e5e9f97f82f766245d4bec33180
parenteb93808fa53d95900ea42b42f8c943c282d99973 (diff)
drivers/intel/gma/opregion: Use CBFS cache to load VBT
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/drivers/intel/gma/Kconfig4
-rw-r--r--src/drivers/intel/gma/opregion.c49
-rw-r--r--src/soc/intel/alderlake/Kconfig4
-rw-r--r--src/soc/intel/jasperlake/Kconfig4
-rw-r--r--src/soc/intel/meteorlake/Kconfig4
-rw-r--r--src/soc/intel/tigerlake/Kconfig4
6 files changed, 24 insertions, 45 deletions
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index 47f7617c34..ca0143d86c 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -59,10 +59,6 @@ config INTEL_GMA_SWSMISCI
config INTEL_GMA_LIBGFXINIT_EDID
bool
-config VBT_DATA_SIZE_KB
- int
- default 8
-
config VBT_CBFS_COMPRESSION_DEFAULT_LZ4
def_bool n
help
diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
index fe333fa674..d5516389e5 100644
--- a/src/drivers/intel/gma/opregion.c
+++ b/src/drivers/intel/gma/opregion.c
@@ -19,40 +19,39 @@ const char *mainboard_vbt_filename(void)
return "vbt.bin";
}
-static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB];
-static size_t vbt_data_sz;
-
void *locate_vbt(size_t *vbt_size)
{
- uint32_t vbtsig = 0;
-
- if (vbt_data_sz != 0) {
- if (vbt_size)
- *vbt_size = vbt_data_sz;
- return (void *)vbt_data;
- }
+ static void *data;
+ static size_t size;
- const char *filename = mainboard_vbt_filename();
+ if (data)
+ goto out;
- size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data));
+ data = cbfs_map(mainboard_vbt_filename(), &size);
+ if (!data || size == 0) {
+ printk(BIOS_ERR, "Could not find or load %s CBFS file\n",
+ mainboard_vbt_filename());
+ goto err;
+ }
- if (file_size == 0)
- return NULL;
+ if (*(uint32_t *)data == VBT_SIGNATURE) {
+ printk(BIOS_INFO, "Found a VBT of %zu bytes\n", size);
+ goto out;
+ }
- if (vbt_size)
- *vbt_size = file_size;
+ printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");
- memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
- if (vbtsig != VBT_SIGNATURE) {
- printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n");
- return NULL;
+err:
+ if (data) {
+ cbfs_unmap(data);
+ data = NULL;
}
+ size = 0;
- printk(BIOS_INFO, "Found a VBT of %zu bytes after decompression\n",
- file_size);
- vbt_data_sz = file_size;
-
- return (void *)vbt_data;
+out:
+ if (vbt_size && size)
+ *vbt_size = size;
+ return data;
}
/* Write ASLS PCI register and prepare SWSCI register. */
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 251695eb4e..eea27fcb6c 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -350,10 +350,6 @@ config CONSOLE_UART_BASE_ADDRESS
default 0xfe03e000
depends on INTEL_LPSS_UART_FOR_CONSOLE
-config VBT_DATA_SIZE_KB
- int
- default 9
-
# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clock * M) /(N *16)
# ADL UART source clock: 100MHz
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 3d84991e09..9f70177ce6 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -174,10 +174,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
-config VBT_DATA_SIZE_KB
- int
- default 9
-
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index d0db3e2b2e..05d7f70256 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -301,10 +301,6 @@ config CONSOLE_UART_BASE_ADDRESS
default 0xfe02c000
depends on INTEL_LPSS_UART_FOR_CONSOLE
-config VBT_DATA_SIZE_KB
- int
- default 9
-
# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clock * M) /(N *16)
# MTL UART source clock: 100MHz
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c07a0d8365..2d5cf08a48 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -222,10 +222,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0x7fff
-config VBT_DATA_SIZE_KB
- int
- default 9
-
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK