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author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-19 23:51:45 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-21 22:26:40 +0000 |
commit | 88615629c051de0833e690463cef6967f0708c0c (patch) | |
tree | 6b7c3ca99d5613e0bdb8c2a5851ec77e005f859d | |
parent | eb723f01afd6fa248560bc6749abd744f3ab3c6c (diff) |
soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16
Change-Id: I97c73324900a0677165afa3f5b182a336d534968
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
-rw-r--r-- | src/soc/amd/cezanne/Kconfig | 4 | ||||
-rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1a38c77b67..83825cd387 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -108,6 +108,10 @@ config MMCONF_BUS_NUMBER int default 64 +config MAX_CPUS + int + default 16 + config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 01dc97e819..9a4aa80ae1 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) +subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr # Beware that all-y also adds the compilation unit to verstage on PSP |