broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`

Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper
code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to
chipset code without having to use `pei_data`. The only mainboard using
LPDDR3 is Google Samus.

Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 40 insertions, 16 deletions

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 3551be1f87..c12d982166 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -1,6 +1,7 @@
 config BOARD_GOOGLE_BASEBOARD_AURON
 	def_bool n
 	select BOARD_ROMSIZE_KB_8192
+	select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c
index b0d9803622..705ec25cd8 100644
--- a/src/mainboard/google/auron/variants/samus/pei_data.c
+++ b/src/mainboard/google/auron/variants/samus/pei_data.c
@@ -1,26 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <stdint.h>
-#include <string.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	/* DQ byte map for Samus board */
-	const u8 dq_map[2][6][2] = {
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
-		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
-		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
-	/* DQS CPU<>DRAM map for Samus board */
-	const u8 dqs_map[2][8] = {
-		{ 2, 0, 1, 3, 6, 4, 7, 5 },
-		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
-
-	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
-	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
-
 	/* P0: HOST PORT */
 	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, USB_PORT_BACK_PANEL);
 	/* P1: HOST PORT */
diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c
index f12744143b..65afe238ed 100644
--- a/src/mainboard/google/auron/variants/samus/spd/spd.c
+++ b/src/mainboard/google/auron/variants/samus/spd/spd.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <mainboard/google/auron/variant.h>
+#include <soc/pei_wrapper.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* Samus board memory configuration GPIOs */
@@ -26,3 +27,20 @@ bool variant_is_dual_channel(const unsigned int spd_index)
 	/* Assume same memory in both channels */
 	return true;
 }
+
+const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void)
+{
+	static const struct lpddr3_dq_dqs_map lpddr3_map = {
+		.dq = {
+			{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+			  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+			{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+			  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+		},
+		.dqs = {
+			{ 2, 0, 1, 3, 6, 4, 7, 5 },
+			{ 2, 1, 0, 3, 6, 5, 4, 7 },
+		},
+	};
+	return &lpddr3_map;
+}
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 4b4df52bf3..3a5b5d52c1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -13,6 +13,12 @@ config SOC_SPECIFIC_OPTIONS
 	select MRC_SETTINGS_PROTECT
 	select REG_SCRIPT
 
+config BROADWELL_LPDDR3
+	bool
+	help
+	  Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific
+	  LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit.
+
 config ECAM_MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
index 80222beccd..cf85c044be 100644
--- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h
+++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
@@ -33,9 +33,17 @@ struct spd_info {
 	unsigned int spd_index;
 };
 
+struct lpddr3_dq_dqs_map {
+	uint8_t dq[2][6][2];
+	uint8_t dqs[2][8];
+};
+
 /* Mainboard callback to fill in the SPD addresses */
 void mb_get_spd_map(struct spd_info *spdi);
 
+/* Mainboard callback to retrieve the LPDDR3-specific DQ/DQS mapping */
+const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void);
+
 void broadwell_fill_pei_data(struct pei_data *pei_data);
 void mainboard_fill_pei_data(struct pei_data *pei_data);
 
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 686c782e2e..d088e5145c 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -196,6 +196,13 @@ void perform_raminit(const struct chipset_power_state *const power_state)
 
 	mainboard_fill_pei_data(&pei_data);
 
+	if (CONFIG(BROADWELL_LPDDR3)) {
+		const struct lpddr3_dq_dqs_map *lpddr3_map = mb_get_lpddr3_dq_dqs_map();
+		assert(lpddr3_map);
+		memcpy(pei_data.dq_map, lpddr3_map->dq, sizeof(pei_data.dq_map));
+		memcpy(pei_data.dqs_map, lpddr3_map->dqs, sizeof(pei_data.dqs_map));
+	}
+
 	/* Obtain the SPD addresses from mainboard code */
 	struct spd_info spdi = { 0 };
 	mb_get_spd_map(&spdi);