diff options
| author | Tim Crawford <tcrawford@system76.com> | 2022-11-28 12:54:24 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 14:29:53 +0000 |
| commit | 5b7b04c938f2647d76abba81cc1e54c9b3508983 (patch) | |
| tree | 98c481712b29cec985f9bd0d69fd243d8728a784 | |
| parent | 1ef3779516bc72abcb3ca722a0cddeb7bbec2105 (diff) | |
mb/system76/cml-u: Convert lemp9 to a variant
Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
31 files changed, 483 insertions, 552 deletions
diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig index 1c1ebbef3d..992f8dc38c 100644 --- a/src/mainboard/system76/cml-u/Kconfig +++ b/src/mainboard/system76/cml-u/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6 +if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_LEMP9 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -10,13 +10,15 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP9 select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO - select PCIEXP_HOTPLUG - select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs + select PCIEXP_HOTPLUG if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 + # Fix running out of MTRRs + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD @@ -29,6 +31,7 @@ config MAINBOARD_DIR config VARIANT_DIR default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -36,16 +39,20 @@ config OVERRIDE_DEVICETREE config MAINBOARD_PART_NUMBER default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Galago Pro" if BOARD_SYSTEM76_GALP4 default "Darter Pro" if BOARD_SYSTEM76_DARP6 + default "Lemur Pro" if BOARD_SYSTEM76_LEMP9 config MAINBOARD_VERSION default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config CBFS_SIZE + default 0xc00000 if BOARD_SYSTEM76_LEMP9 default 0xA00000 config CONSOLE_POST diff --git a/src/mainboard/system76/cml-u/Kconfig.name b/src/mainboard/system76/cml-u/Kconfig.name index 30478cac8c..258ee082d7 100644 --- a/src/mainboard/system76/cml-u/Kconfig.name +++ b/src/mainboard/system76/cml-u/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_SYSTEM76_GALP4 config BOARD_SYSTEM76_DARP6 bool "darp6" + +config BOARD_SYSTEM76_LEMP9 + bool "lemp9" diff --git a/src/mainboard/system76/cml-u/Makefile.inc b/src/mainboard/system76/cml-u/Makefile.inc index d749e412cc..52763089db 100644 --- a/src/mainboard/system76/cml-u/Makefile.inc +++ b/src/mainboard/system76/cml-u/Makefile.inc @@ -4,5 +4,7 @@ bootblock-y += bootblock.c bootblock-y += gpio_early.c ramstage-y += ramstage.c -ramstage-y += gpio.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + +SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index da86024f50..86e7aa4e67 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -70,31 +70,14 @@ chip soc/intel/cannonlake device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT - end device pci 14.1 off end # USB xDCI (OTG) device pci 14.3 on # CNVi wifi chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" + register "wake" = "GPE0_PME_B0" device generic 0 on end end end device pci 14.5 off end # SDCard - device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 @@ -104,52 +87,23 @@ chip soc/intel/cannonlake device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" - end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 - # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpHotPlug[4]" = "1" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcClkReq[4]" = "4" - end + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 - # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "8" - register "PcieClkSrcClkReq[3]" = "3" - end - device pci 1d.1 on # PCI Express Port 10 - # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[5]" = "12" - register "PcieClkSrcClkReq[5]" = "5" - end + device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 @@ -169,8 +123,6 @@ chip soc/intel/cannonlake device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "1" - register "PchHdaAudioLinkDmic1" = "1" end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/system76/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex index f747f7c34e..f747f7c34e 100644 --- a/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex +++ b/src/mainboard/system76/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex diff --git a/src/mainboard/system76/cml-u/gpio.c b/src/mainboard/system76/cml-u/variants/darp6/gpio.c index 03683ae7b9..41353a9acc 100644 --- a/src/mainboard/system76/cml-u/gpio.c +++ b/src/mainboard/system76/cml-u/variants/darp6/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <mainboard/gpio.h> -#include <soc/gpe.h> #include <soc/gpio.h> static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 631803c68a..a39622cea3 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -1,7 +1,24 @@ chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1404 inherit - device pci 15.0 on + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + end + device pci 15.0 on # I2C #0 chip drivers/i2c/hid register "generic.hid" = ""SYNA1202"" register "generic.desc" = ""Synaptics Touchpad"" @@ -10,6 +27,43 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end - end # I2C #0 + end + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.0 on # PCI Express Port 9 + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.1 on # PCI Express Port 10 + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1d.4 on # PCI Express Port 13 + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + end + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + end end end diff --git a/src/mainboard/system76/cml-u/romstage.c b/src/mainboard/system76/cml-u/variants/darp6/romstage.c index 1cd82c6491..aae639b437 100644 --- a/src/mainboard/system76/cml-u/romstage.c +++ b/src/mainboard/system76/cml-u/variants/darp6/romstage.c @@ -6,11 +6,11 @@ static const struct cnl_mb_cfg memcfg = { .spd[0] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, + .spd_spec = { .spd_smbus_address = 0xa0 }, }, .spd[2] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, + .spd_spec = { .spd_smbus_address = 0xa4 }, }, .rcomp_resistor = { 121, 81, 100 }, .rcomp_targets = { 100, 40, 20, 20, 26 }, diff --git a/src/mainboard/system76/cml-u/variants/galp4/gpio.c b/src/mainboard/system76/cml-u/variants/galp4/gpio.c new file mode 100644 index 0000000000..41353a9acc --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/galp4/gpio.c @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_NC(GPD0, NONE), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_CFG_GPI(GPD7, NONE, DEEP), // 100k pull up + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK + PAD_NC(GPD9, NONE), // GPD9_RTD3 + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* ------- GPIO Group A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ with 10k pull up + PAD_CFG_GPI(GPP_A7, NONE, DEEP), // TPM_PIRQ# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# with 8.2k pull-up + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // PCLK_KBC + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), // PCH_GPP_A12 + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_NC(GPP_A14, NONE), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK + PAD_NC(GPP_A16, NONE), + PAD_CFG_GPI(GPP_A17, NONE, DEEP), // LIGHT_KB_DET# + PAD_NC(GPP_A18, NONE), + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SATA_PWR_EN + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 0, DEEP), // PS8338B_SW + PAD_CFG_GPO(GPP_A23, 0, DEEP), // PS8338B_PCH + + /* ------- GPIO Group B ------- */ + PAD_NC(GPP_B0, NONE), // CORE_VID0 + PAD_NC(GPP_B1, NONE), // CORE_VID1 + PAD_CFG_GPO(GPP_B2, 0, DEEP), // CNVI_WAKE# + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_B11, NONE), // EXT_PWR_GATE# + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# with 100k pull down + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 + PAD_NC(GPP_B17, NONE), // PCH_GPP_B17 + PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - strap for disabling no reboot mode + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Group C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT_DDR + PAD_NC(GPP_C2, NONE), // PCH_GPP_C2 with 4.7k pull-up + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 with 4.7k pull down + PAD_CFG_GPI(GPP_C6, NONE, DEEP), // LAN_WAKEUP# + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBCIO_PLUG_EVENT + PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // TBT_FRC_PWR + PAD_NC(GPP_C11, NONE), + PAD_CFG_GPO(GPP_C12, 1, PLTRST), // GPP_C12_RTD3 + PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD_PWR_DN# + PAD_CFG_GPO(GPP_C14, 0, PLTRST), // TBTA_HRESET + PAD_CFG_GPO(GPP_C15, 1, PLTRST), // TBT_PERST_N + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), // SWI# on galp4, NC on darp6 + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST), // NC on galp4, TP_ATTN# on darp6 + + /* ------- GPIO Group D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_CFG_GPO(GPP_D8, 1, DEEP), // SB_BLON + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // SWI# + PAD_NC(GPP_D10, NONE), + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), // RTD3_PCIE_WAKE# + PAD_NC(GPP_D12, NONE), // PCH_GPP_D12 + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_CFG_GPO(GPP_D15, 1, DEEP), // TBT_RTD3_PWR_EN_D15 on galp4, NC on darp6 + PAD_CFG_GPO(GPP_D16, 1, PWROK), // RTD3_3G_PW R_EN on galp4, NC on darp6 + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // GPPC_DMIC_CLK + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // GPPC_DMIC_DATA + PAD_CFG_GPI(GPP_D21, NONE, DEEP), // TPM_DET# + PAD_CFG_GPI(GPP_D22, NONE, DEEP), // TPM_TCM_Detect + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group E ------- */ + PAD_NC(GPP_E0, NONE), // PCH_GPP_E0 with 10k pull-up + PAD_NC(GPP_E1, NONE), // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), // SATAGP2 + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), // DEVSLP2 + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_NC(GPP_E9, NONE), // GP_BSSB_CLK + PAD_NC(GPP_E10, NONE), // GPP_E10 + PAD_NC(GPP_E11, NONE), // GPP_E11 + PAD_NC(GPP_E12, NONE), // USB_OC#78 + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), // MUX_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SMI# + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // SCI# + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), // MDP_CTRLCLK + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), // MDP_CTRLDATA + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPI(GPP_F23, NONE, DEEP), // A4WP_PRESENT + + /* ------- GPIO Group G ------- */ + PAD_CFG_GPI(GPP_G0, NONE, DEEP), // EDP_DET + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPO(GPP_G3, 0, DEEP), // ASM1543_I_SEL0 + PAD_CFG_GPO(GPP_G4, 0, DEEP), // ASM1543_I_SEL1 + PAD_NC(GPP_G5, NONE), // BOARD_ID + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), // TBT_Detect + + /* ------- GPIO Group H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_RST# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), // G_INT1 + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), // GPPC_H21 + PAD_CFG_GPO(GPP_H22, 1, DEEP), // TBT_RTD3_PWR_EN_H22 + PAD_NC(GPP_H23, NONE), // WIGIG_PEWAKE on galp4, NC on darp6 +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index f6c61498be..f6be0eb358 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -1,8 +1,62 @@ chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1403 inherit - device pci 15.0 on + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + end + device pci 15.0 on # I2C #0 # I2C HID not supported on galp4 - end # I2C #0 + end + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.0 on # PCI Express Port 9 + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.1 on # PCI Express Port 10 + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1d.4 on # PCI Express Port 13 + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + end + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + end end end diff --git a/src/mainboard/system76/cml-u/variants/galp4/romstage.c b/src/mainboard/system76/cml-u/variants/galp4/romstage.c new file mode 100644 index 0000000000..aae639b437 --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/galp4/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = { .spd_smbus_address = 0xa0 }, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = { .spd_smbus_address = 0xa4 }, + }, + .rcomp_resistor = { 121, 81, 100 }, + .rcomp_targets = { 100, 40, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt new file mode 100644 index 0000000000..c547c6abef --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt @@ -0,0 +1,2 @@ +Board name: lemp9 +Release year: 2020 diff --git a/src/mainboard/system76/lemp9/data.vbt b/src/mainboard/system76/cml-u/variants/lemp9/data.vbt Binary files differindex f14d8073e9..f14d8073e9 100644 --- a/src/mainboard/system76/lemp9/data.vbt +++ b/src/mainboard/system76/cml-u/variants/lemp9/data.vbt diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c index 59d8d063d9..d27acadbfa 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c @@ -1,23 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h> -#ifndef __ACPI__ - -/* Name format: <pad name> / <net/pin name in schematics> */ - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - PAD_NC(GPP_C22, UP_20K), - PAD_NC(GPP_C23, UP_20K), -}; - -/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPD ------- */ PAD_NC(GPD0, NONE), @@ -248,6 +233,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H23, UP_20K), }; -#endif - -#endif +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c index 1b9386d388..1b9386d388 100644 --- a/src/mainboard/system76/lemp9/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb new file mode 100644 index 0000000000..e85cf63623 --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/cannonlake + device domain 0 on + subsystemid 0x1558 0x1401 inherit + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 + end + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""ELAN040D"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 2 (J_SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 3 (J_SSD1) + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 Card reader + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpSlotImplemented[5]" = "1" + end + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" + chip drivers/wifi/generic + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + end +end diff --git a/src/mainboard/system76/cml-u/variants/lemp9/romstage.c b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c new file mode 100644 index 0000000000..2be3353d40 --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SPD_CBFS, + .spd_spec = { .spd_index = 0 }, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = { .spd_smbus_address = 0xa4 }, + }, + .rcomp_resistor = { 121, 81, 100 }, + .rcomp_targets = { 100, 40, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig deleted file mode 100644 index dbc9de20b8..0000000000 --- a/src/mainboard/system76/lemp9/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -if BOARD_SYSTEM76_LEMP9 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_HID - select EC_SYSTEM76_EC - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE - select HAVE_SMI_HANDLER - select HAVE_SPD_IN_CBFS - select INTEL_GMA_HAVE_VBT - select INTEL_LPSS_UART_FOR_CONSOLE - select MEMORY_MAPPED_TPM - select MAINBOARD_HAS_TPM2 - select NO_UART_ON_SUPERIO - select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP - select TPM_MEASURED_BOOT - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB - -config MAINBOARD_DIR - default "system76/lemp9" - -config MAINBOARD_PART_NUMBER - default "lemp9" - -config MAINBOARD_SMBIOS_PRODUCT_NAME - string - default "Lemur Pro" - -config MAINBOARD_VERSION - string - default "lemp9" - -config CBFS_SIZE - default 0xc00000 - -config CONSOLE_POST - bool - default y - -config UART_FOR_CONSOLE - int - default 2 - -config DIMM_MAX - default 2 - -config VGA_BIOS_ID - string - default "8086,9b41" - -config TPM_PIRQ - hex - default 0x10 # GPP_A7/PIRQA# - -config POST_DEVICE - bool - default n - -endif diff --git a/src/mainboard/system76/lemp9/Kconfig.name b/src/mainboard/system76/lemp9/Kconfig.name deleted file mode 100644 index 4a4ab68597..0000000000 --- a/src/mainboard/system76/lemp9/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SYSTEM76_LEMP9 - bool "lemp9" diff --git a/src/mainboard/system76/lemp9/Makefile.inc b/src/mainboard/system76/lemp9/Makefile.inc deleted file mode 100644 index 3d742d6e13..0000000000 --- a/src/mainboard/system76/lemp9/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -bootblock-y += bootblock.c -ramstage-y += ramstage.c -ramstage-y += hda_verb.c -SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl deleted file mode 100644 index c1bc04dc9a..0000000000 --- a/src/mainboard/system76/lemp9/acpi/gpe.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// GPP_D9 SCI -Method (_L29, 0, Serialized) { - Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) - If (\_SB.PCI0.LPCB.EC0.ECOK) { - If (\_SB.PCI0.LPCB.EC0.WFNO == One) { - Notify(\_SB.LID0, 0x80) - } - } -} diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl deleted file mode 100644 index 416cc5a151..0000000000 --- a/src/mainboard/system76/lemp9/acpi/mainboard.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define EC_GPE_SCI 0x50 /* GPP_E16 */ -#define EC_GPE_SWI 0x29 /* GPP_D9 */ -#include <ec/system76/ec/acpi/ec.asl> - -Scope (\_SB) { - #include "sleep.asl" -} - -Scope (\_GPE) { - #include "gpe.asl" -} diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl deleted file mode 100644 index 48c50e075e..0000000000 --- a/src/mainboard/system76/lemp9/acpi/sleep.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) { - \_SB.PCI0.LPCB.EC0.PTS (Arg0) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) { - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/system76/lemp9/board_info.txt b/src/mainboard/system76/lemp9/board_info.txt deleted file mode 100644 index f6784eff02..0000000000 --- a/src/mainboard/system76/lemp9/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Vendor name: System76 -Board name: lemp9 -Category: laptop -Release year: 2020 -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c deleted file mode 100644 index fd6070c06b..0000000000 --- a/src/mainboard/system76/lemp9/bootblock.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <gpio.h> -#include "gpio.h" - -void bootblock_mainboard_early_init(void) -{ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default deleted file mode 100644 index 0d376751c1..0000000000 --- a/src/mainboard/system76/lemp9/cmos.default +++ /dev/null @@ -1,3 +0,0 @@ -boot_option=Fallback -debug_level=Debug -me_state=Disable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout deleted file mode 100644 index a53c3f4bba..0000000000 --- a/src/mainboard/system76/lemp9/cmos.layout +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -entries - -0 384 r 0 reserved_memory - -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# RTC_CLK_ALTCENTURY -400 8 r 0 century - -412 4 e 6 debug_level -416 1 e 2 me_state -417 3 h 0 me_state_counter -984 16 h 0 check_sum - -enumerations - -2 0 Enable -2 1 Disable - -4 0 Fallback -4 1 Normal - -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 408 983 984 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb deleted file mode 100644 index 77ba265ea9..0000000000 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ /dev/null @@ -1,201 +0,0 @@ -chip soc/intel/cannonlake - register "common_soc_config" = "{ - /* Touchpad */ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 80, - .fall_time_ns = 110, - }, - }" - -# CPU (soc/intel/cannonlake/cpu.c) - # Power limit - register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, - }" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART - }" - - # Misc - register "AcousticNoiseMitigation" = "1" - #register "dmipwroptimize" = "1" - #register "satapwroptimize" = "1" - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "12" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - subsystemid 0x1558 0x1401 inherit - device pci 00.0 on end # Host Bridge - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN040D"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "SataSalpSupport" = "1" - # Port 2 (J_SSD2) - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - # Port 3 (J_SSD1) - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" - end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on # PCI Express Port 6 - device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[3]" = "5" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[5]" = "1" - end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 - device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieClkSrcUsage[2]" = "7" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieRpSlotImplemented[7]" = "1" - chip drivers/wifi/generic - device pci 00.0 on end - end - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" - end - device pci 1d.0 on # PCI Express Port 9 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[4]" = "8" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieRpSlotImplemented[8]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[5]" = "12" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieRpSlotImplemented[12]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" - end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen1_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen2_dec" = "0x00fc0E01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen3_dec" = "0x00fc0F01" - chip drivers/pc80/tpm # TPM - device pnp 0c31.0 on end - end - end - device pci 1f.1 off end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA - register "PchHdaAudioLinkHda" = "1" - end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl deleted file mode 100644 index b633254edd..0000000000 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include <soc/intel/common/block/acpi/acpi/platform.asl> - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> - - Device (\_SB.PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/cannonlake/acpi/southbridge.asl> - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> - - Scope (\_SB.PCI0.LPCB) - { - #include <drivers/pc80/pc/ps2_controller.asl> - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c deleted file mode 100644 index a5ada97e5d..0000000000 --- a/src/mainboard/system76/lemp9/ramstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/ramstage.h> -#include "gpio.h" -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} - -void mainboard_silicon_init_params(FSPS_UPD *supd) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c deleted file mode 100644 index 3b9c896f1b..0000000000 --- a/src/mainboard/system76/lemp9/romstage.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/cnl_memcfg_init.h> -#include <soc/romstage.h> - -static const struct cnl_mb_cfg memcfg = { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ - .spd[0] = { - .read_type = READ_SPD_CBFS, - .spd_spec = {.spd_index = 0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ - .rcomp_resistor = { 121, 81, 100 }, - - /* Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - .dq_pins_interleaved = 1, - - /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. - */ - .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, -}; - -void mainboard_memory_init_params(FSPM_UPD *memupd) -{ - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); -} |