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authorV Sowmya <v.sowmya@intel.com>2020-12-03 23:18:55 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-12-04 07:05:43 +0000
commit407488edaa157d3d06e0aab6578b006641ca8256 (patch)
tree9bc3c51d43419372d061b670cf38442fe28e8227
parentfef413e4be6e3b4e277238aaca56886e50dbfcde (diff)
src/soc/intel/alderlake: Enable the PCH HDA
This patch enables the PCH HDA device based on the devicetree configuration. Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 868d75e9da..7e842a200c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -100,6 +100,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+ m_cfg->PchHdaEnable = is_dev_enabled(dev);
+
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,