Add pci_devfn_t and use with __SIMPLE_DEVICE__

Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.

Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

16 files changed, 45 insertions, 38 deletions

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 3b61e85b07..859146578b 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -210,7 +210,10 @@ static inline int log2f(int value)
 
 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
 
-typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
+/* FIXME: Sources for romstage still use device_t. */
+typedef u32 device_t;
+
+typedef u32 pci_devfn_t;
 
 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
  * We don't need to set %fs, and %gs anymore
@@ -220,23 +223,26 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha
 #include <arch/pci_io_cfg.h>
 #include <arch/pci_mmio_cfg.h>
 
-static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value)
+static inline __attribute__((always_inline))
+void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value)
 {
 	pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
 }
 
-static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value)
+static inline __attribute__((always_inline))
+void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value)
 {
 	pci_write_config16(dev, where, pci_read_config16(dev, where) | value);
 }
 
-static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value)
+static inline __attribute__((always_inline))
+void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value)
 {
 	pci_write_config32(dev, where, pci_read_config32(dev, where) | value);
 }
 
 #define PCI_DEV_INVALID (0xffffffffU)
-static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
+static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev)
 {
         for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
                 unsigned int id;
@@ -248,7 +254,7 @@ static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
         return PCI_DEV_INVALID;
 }
 
-static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
+static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev)
 {
 	for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
@@ -260,9 +266,9 @@ static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
 	return PCI_DEV_INVALID;
 }
 
-static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
 {
-	device_t dev, last;
+	pci_devfn_t dev, last;
 
         dev = PCI_DEV(bus, 0, 0);
         last = PCI_DEV(bus, 31, 7);
diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h
index fbe83a2b47..63e1ac958c 100644
--- a/src/arch/x86/include/arch/pci_io_cfg.h
+++ b/src/arch/x86/include/arch/pci_io_cfg.h
@@ -21,7 +21,7 @@
 #include <arch/io.h>
 
 static inline __attribute__((always_inline))
-uint8_t pci_io_read_config8(device_t dev, unsigned where)
+uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned where)
 {
 	unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
@@ -34,7 +34,7 @@ uint8_t pci_io_read_config8(device_t dev, unsigned where)
 }
 
 static inline __attribute__((always_inline))
-uint16_t pci_io_read_config16(device_t dev, unsigned where)
+uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned where)
 {
 	unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
@@ -47,7 +47,7 @@ uint16_t pci_io_read_config16(device_t dev, unsigned where)
 }
 
 static inline __attribute__((always_inline))
-uint32_t pci_io_read_config32(device_t dev, unsigned where)
+uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned where)
 {
 	unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
@@ -60,7 +60,7 @@ uint32_t pci_io_read_config32(device_t dev, unsigned where)
 }
 
 static inline __attribute__((always_inline))
-void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
+void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value)
 {
 	unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
@@ -73,7 +73,7 @@ void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
 }
 
 static inline __attribute__((always_inline))
-void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
+void pci_io_write_config16(pci_devfn_t dev, unsigned where, uint16_t value)
 {
         unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
@@ -86,7 +86,7 @@ void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
 }
 
 static inline __attribute__((always_inline))
-void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
+void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value)
 {
 	unsigned addr;
 #if !CONFIG_PCI_IO_CFG_EXT
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
index 545be236c2..b62a2166b9 100644
--- a/src/arch/x86/include/arch/pci_mmio_cfg.h
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -26,7 +26,7 @@
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
 
 static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
+u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | where;
@@ -34,7 +34,7 @@ u8 pcie_read_config8(device_t dev, unsigned int where)
 }
 
 static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
+u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
@@ -42,7 +42,7 @@ u16 pcie_read_config16(device_t dev, unsigned int where)
 }
 
 static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
+u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
@@ -50,7 +50,7 @@ u32 pcie_read_config32(device_t dev, unsigned int where)
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | where;
@@ -58,7 +58,7 @@ void pcie_write_config8(device_t dev, unsigned int where, u8 value)
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
@@ -66,7 +66,7 @@ void pcie_write_config16(device_t dev, unsigned int where, u16 value)
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
 {
 	unsigned long addr;
 	addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
@@ -74,21 +74,21 @@ void pcie_write_config32(device_t dev, unsigned int where, u32 value)
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask)
 {
 	u8 value = pcie_read_config8(dev, where);
 	pcie_write_config8(dev, where, value | ormask);
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask)
 {
 	u16 value = pcie_read_config16(dev, where);
 	pcie_write_config16(dev, where, value | ormask);
 }
 
 static inline __attribute__ ((always_inline))
-void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask)
 {
 	u32 value = pcie_read_config32(dev, where);
 	pcie_write_config32(dev, where, value | ormask);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 797e7179b2..1056be775b 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -11,6 +11,7 @@ struct device;
 
 #ifndef __SIMPLE_DEVICE__
 typedef struct device * device_t;
+typedef u32 pci_devfn_t;
 struct pci_operations;
 struct pci_bus_operations;
 struct smbus_bus_operations;
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 4590544765..28e947b393 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -85,7 +85,7 @@ u32 decode_igd_gtt_size(const u32 gsm)
 
 u32 get_top_of_ram(void)
 {
-	const device_t dev = PCI_DEV(0, 0, 0);
+	const pci_devfn_t dev = PCI_DEV(0, 0, 0);
 
 	u32 tor;
 
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index 36f96d3767..16c56a2c83 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -36,7 +36,7 @@ static inline void set_bios_reset(void)
 {
 	u32 nodes;
 	u32 htic;
-	device_t dev;
+	pci_devfn_t dev;
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 36f96d3767..16c56a2c83 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -36,7 +36,7 @@ static inline void set_bios_reset(void)
 {
 	u32 nodes;
 	u32 htic;
-	device_t dev;
+	pci_devfn_t dev;
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 48799040af..198066fd03 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -36,7 +36,7 @@
  */
 u32 get_sbdn(u32 bus)
 {
-	device_t dev;
+	pci_devfn_t dev;
 
 	printk(BIOS_SPEW, "SB900 - Early.c - get_sbdn - Start.\n");
 
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 36f96d3767..16c56a2c83 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -36,7 +36,7 @@ static inline void set_bios_reset(void)
 {
 	u32 nodes;
 	u32 htic;
-	device_t dev;
+	pci_devfn_t dev;
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c
index 0e4b4240c0..d20c8c4fe1 100644
--- a/src/southbridge/amd/sb600/enable_usbdebug.c
+++ b/src/southbridge/amd/sb600/enable_usbdebug.c
@@ -34,7 +34,7 @@ void set_debug_port(unsigned int port)
 
 void enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+	pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
 
 	/* Select the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index f0efe412ea..00eb4d924b 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -49,7 +49,7 @@ void set_debug_port(unsigned int port)
  */
 void enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
+	pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index e457368370..ae79c4a440 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -36,7 +36,7 @@ static void set_bios_reset(void)
 {
 	u32 nodes;
 	u32 htic;
-	device_t dev;
+	pci_devfn_t dev;
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index d140123da3..6b934f4fa0 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -35,7 +35,7 @@ void set_debug_port(unsigned int port)
 void enable_usbdebug(unsigned int port)
 {
 	u32 dbgctl;
-	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+	pci_devfn_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 54b534ee6a..90890e6802 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -39,7 +39,7 @@
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -50,7 +50,7 @@ void set_debug_port(unsigned int port)
 
 void enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index ec066538ce..069344b522 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -33,7 +33,7 @@
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -44,7 +44,7 @@ void set_debug_port(unsigned int port)
 
 void enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index 1ff04dfbc0..f38fe90398 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -35,7 +35,7 @@
 void set_debug_port(unsigned int port)
 {
 	u32 dword;
-	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Write the port number to 0x74[15:12]. */
 	dword = pci_read_config32(dev, 0x74);
@@ -46,7 +46,7 @@ void set_debug_port(unsigned int port)
 
 void enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
+	pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
 
 	/* Mark the requested physical USB port (1-15) as the Debug Port. */
 	set_debug_port(port);