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authorFelix Singer <felixsinger@posteo.net>2024-06-23 03:56:43 +0200
committerFelix Singer <felixsinger@posteo.net>2024-06-24 14:22:46 +0000
commit0c1daa59b902364d26f13290dff0e44bda839539 (patch)
treeb9d4edc690126b00001714f6cea64a7f41f500cb
parent1a77d1e437c7dc4efd8ab665ccf1ed9d18ba835d (diff)
skl mainboards/dt: Drop SsicPortEnable setting if disabled
The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb1
-rw-r--r--src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb1
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb2
-rw-r--r--src/mainboard/google/eve/devicetree.cb1
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb1
-rw-r--r--src/mainboard/libretrend/lt1000/devicetree.cb1
-rw-r--r--src/mainboard/protectli/vault_kbl/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb1
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/devicetree.cb1
17 files changed, 0 insertions, 18 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index b25e357813..83f8e6e563 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[2]" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
index cb6d409164..f0588da850 100644
--- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
- register "SsicPortEnable" = "0"
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index fdb59c9fcf..bf634c513d 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -197,8 +197,6 @@ chip soc/intel/skylake
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
- register "SsicPortEnable" = "0"
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 8b4718d0f1..62a5ac225b 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index ec11060618..c6ec0856c3 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -71,7 +71,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[1]" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2c34beb3bd..789d49a474 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index e5220414ea..e661f3ac84 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index cfeefb1d72..5f8b4593a5 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index e5cbdcc66e..ea753bf737 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index ad22c77075..aebec9ff6e 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 7c0abc141c..a5db866707 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index dce0a89399..786354e696 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index feaa7751be..d274e15be1 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 9d7dedf5d8..9c4a3661c2 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataSpeedLimit" = "2"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index c5a2c569b6..503a491263 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -31,7 +31,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index f844a5283e..acff2823c6 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[2]" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index e8da7af3e0..e405114769 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -30,7 +30,6 @@ chip soc/intel/skylake
}"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
- register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"