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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-24 18:06:26 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-29 10:20:47 +0000 |
| commit | 0a54685b295a8dc9180e011a6e1067d178636427 (patch) | |
| tree | 0fdd6a9f802710ac8b02a4e879785fbce7220709 | |
| parent | d0bc92df73d7653ed8b6c76baf3a39c7f8f37173 (diff) | |
drivers/intel/fsp1_1: Drop s3_resume parameter to load_vbt()
Change-Id: Iaba88026906132b96fe3db3f05950df0e7eef896
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/vbt.c | 5 |
3 files changed, 5 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index f925088e00..50e3bd6fad 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -18,6 +18,6 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params); -void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); +void load_vbt(SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 5fff60ac1a..45faa5507e 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -82,7 +82,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) /* Locate VBT and pass to FSP GOP */ if (CONFIG(RUN_FSP_GOP)) - load_vbt(is_s3_wakeup, &silicon_init_params); + load_vbt(&silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup) diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 88f14ee85a..37471e5c83 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <bootmode.h> #include <console/console.h> #include <drivers/intel/gma/opregion.h> @@ -8,13 +9,13 @@ #include <lib.h> /* Locate VBT and pass it to FSP GOP */ -void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params) +void load_vbt(SILICON_INIT_UPD *params) { const optionrom_vbt_t *vbt_data = NULL; size_t vbt_len; /* Check boot mode - for S3 resume path VBT loading is not needed */ - if (s3_resume) { + if (acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); } else if (display_init_required()) { /* Get VBT data */ |