diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-13 13:05:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:20:38 +0000 |
| commit | 06d224f65ee265f724f915dcbab0486773b7c6da (patch) | |
| tree | fd12cea016d3cf6cffc4e479f5c08795b42262c8 | |
| parent | 082f0b94ee1a6a6a06c6c6315c815b0c16274281 (diff) | |
nb/intel/x4x: Correct DDR3 turnaround table
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.
Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.
Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Tested-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 16e257fc28..2389b5f899 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -428,22 +428,22 @@ static void program_timings(struct sysinfo *s) static const u8 ddr3_turnaround_tab[3][6][4] = { { /* DDR3 800 */ - {0x9, 0x7, 0x7, 0x9}, /* CL = 5 */ + {0x9, 0x7, 0x9, 0x7}, /* CL = 5 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 6 */ }, { /* DDR3 1066 */ {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ - {0x9, 0x7, 0x7, 0x9}, /* CL = 6 */ + {0x9, 0x7, 0x9, 0x7}, /* CL = 6 */ {0x9, 0x7, 0x8, 0x8}, /* CL = 7 */ - {0x9, 0x7, 0x9, 0x7} /* CL = 8 */ + {0x9, 0x7, 0x7, 0x9} /* CL = 8 */ }, { /* DDR3 1333 */ {0x0, 0x0, 0x0, 0x0}, /* CL = 5 - Not supported */ {0x0, 0x0, 0x0, 0x0}, /* CL = 6 - Not supported */ {0x0, 0x0, 0x0, 0x0}, /* CL = 7 - Not supported */ - {0x9, 0x7, 0x9, 0x8}, /* CL = 8 */ - {0x9, 0x7, 0xA, 0x7}, /* CL = 9 */ - {0x9, 0x7, 0xB, 0x6}, /* CL = 10 */ + {0x9, 0x7, 0x8, 0x9}, /* CL = 8 */ + {0x9, 0x7, 0x7, 0xa}, /* CL = 9 */ + {0x9, 0x7, 0x6, 0xb}, /* CL = 10 */ } }; |