1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Include this file into a mainboard's DSDT _SB device tree and it will
* expose the SCH5147 SuperIO and some of its functionality.
*
* It allows the change of IO ports, IRQs and DMA settings on logical
* devices, disabling and reenabling logical devices and controlling power
* saving mode on logical devices or the whole chip.
*
* LDN State
* 0x0 FDC Not implemented
* 0x3 PP Not implemented
* 0x4 UARTA Implemented
* 0x5 UARTB Implemented
* 0x7 KBC Implemented
* 0xa Runtime reg Not implemented
*
* Controllable through preprocessor defines:
* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
* SUPERIO_PNP_BASE I/o address of the first PnP configuration register
* SCH5147_SHOW_UARTA If defined, UARTA will be exposed.
* SCH5147_SHOW_UARTB If defined, UARTB will be exposed.
* SCH5147_SHOW_KBC If defined, the KBC will be exposed.
*/
#undef SUPERIO_CHIP_NAME
#define SUPERIO_CHIP_NAME SCH5147
#include <superio/acpi/pnp.asl>
#undef PNP_DEFAULT_PSC
#define PNP_DEFAULT_PSC Return (0) /* no power management */
Device(SUPERIO_DEV) {
Name (_HID, EisaId("PNP0A05"))
Name (_STR, Unicode("SMSC SCH5147 Super I/O"))
Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
/* Mutex for accesses to the configuration ports */
Mutex(CRMX, 1)
/* SuperIO configuration ports */
OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
}
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{
Offset (0x07),
PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
Offset (0x30),
PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
Offset (0x60),
PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
Offset (0x62),
PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
Offset (0x70),
PNP_IRQ0, 8, /* First IRQ */
Offset (0x72),
PNP_IRQ1, 8, /* Second IRQ */
Offset (0x74),
PNP_DMA0, 8, /* DMA */
}
Method (_CRS)
{
/* Announce the used i/o ports to the OS */
Return (ResourceTemplate () {
IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
})
}
#undef PNP_ENTER_MAGIC_1ST
#undef PNP_ENTER_MAGIC_2ND
#undef PNP_ENTER_MAGIC_3RD
#undef PNP_ENTER_MAGIC_4TH
#undef PNP_EXIT_MAGIC_1ST
#undef PNP_EXIT_SPECIAL_REG
#undef PNP_EXIT_SPECIAL_VAL
#define PNP_ENTER_MAGIC_1ST 0x55
#define PNP_EXIT_MAGIC_1ST 0xaa
#include <superio/acpi/pnp_config.asl>
#ifdef SCH5147_SHOW_UARTA
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 4
#include <superio/acpi/pnp_uart.asl>
#endif
#ifdef SCH5147_SHOW_UARTB
#undef SUPERIO_UART_LDN
#undef SUPERIO_UART_DDN
#undef SUPERIO_UART_PM_REG
#undef SUPERIO_UART_PM_VAL
#undef SUPERIO_UART_PM_LDN
#define SUPERIO_UART_LDN 5
#include <superio/acpi/pnp_uart.asl>
#endif
#ifdef SCH5147_SHOW_KBC
/* we can't read back the IO resources so hardcode them */
#define SUPERIO_KBC_LDN 7
Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
Name (_HID, EisaId ("PNP0303"))
Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN))
Method (_STA)
{
PNP_GENERIC_STA(SUPERIO_KBC_LDN)
}
Method (_DIS)
{
ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
PNP_DEVICE_ACTIVE = 0
EXIT_CONFIG_MODE ()
#if defined(SUPERIO_KBC_PS2LDN)
Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
#elif defined(SUPERIO_KBC_PS2M)
Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
#endif
}
Method (_PSC) {
PNP_DEFAULT_PSC
}
Method (_CRS, 0, Serialized)
{
Name (CRS, ResourceTemplate () {
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags (IR0) {}
})
ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
EXIT_CONFIG_MODE ()
Return (CRS)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0,0) {
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags () {1}
}
EndDependentFn()
})
Method (_SRS, 1, Serialized)
{
Name (TMPL, ResourceTemplate () {
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
IRQNoFlags (IR0) {}
})
ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
PNP_DEVICE_ACTIVE = 1
EXIT_CONFIG_MODE ()
Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
}
}
Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
Name (_HID, EisaId ("PNP0F13"))
Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN))
Method (_STA)
{
Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ())
}
Method (_PSC) {
Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ())
}
Method (_CRS, 0, Serialized)
{
Name (CRS, ResourceTemplate () {
IRQNoFlags (IR1) {}
})
ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
EXIT_CONFIG_MODE ()
Return (CRS)
}
Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0,0) {
IRQNoFlags () {12}
}
EndDependentFn()
})
Method (_SRS, 1, Serialized)
{
Name (TMPL, ResourceTemplate () {
IRQNoFlags (IR1) {}
})
ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
EXIT_CONFIG_MODE ()
}
}
#endif
}
|
