blob: bba89f4699fd6103d6f3b412f90983063d376fdd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
bootblock-y += bootblock.c
ramstage-y += pch.c
ramstage-y += iobp.c
ramstage-y += azalia.c
ramstage-y += fadt.c
ramstage-y += lpc.c
ramstage-y += pcie.c
ramstage-y += sata.c
ramstage-y += usb_ehci.c
ramstage-y += usb_xhci.c
ramstage-y += me.c
ramstage-y += smbus.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c
ifneq ($(CONFIG_VARIANT_DIR),)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/hda_verb.c
endif
ramstage-y += me_status.c
ramstage-y += acpi.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
smm-y += smihandler.c pch.c
smm-y += pmutil.c usb_ehci.c usb_xhci.c
bootblock-y += early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c
smm-y += lp_gpio.c
verstage-y += lp_gpio.c
bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += uart_init.c
bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += iobp.c
all-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c
smm-$(CONFIG_SERIALIO_UART_CONSOLE) += uart.c
endif
verstage-y += pmutil.c
CPPFLAGS_common += -I$(src)/southbridge/intel/lynxpoint/include
endif
|
