blob: 70b2734797e6e8e44410cc9b5eb8791dac7cc3fa (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
## Copyright (C) 2013 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOUTHBRIDGE_INTEL_FSP_BD82X6X
bool
if SOUTHBRIDGE_INTEL_FSP_BD82X6X
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
config EHCI_BAR
hex
default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/fsp_bd82x6x/bootblock.c"
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
config HPET_MIN_TICKS
hex
default 0x80
endif
|
