blob: 4ee1ac0a0d08c3c36f7dd63bc81d2d65bc0a305a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <stdint.h>
#include <intelblocks/cfg.h>
#include <soc/gpio.h>
#include <soc/irq.h>
struct soc_intel_xeon_sp_skx_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
*/
uint8_t pirqa_routing;
uint8_t pirqb_routing;
uint8_t pirqc_routing;
uint8_t pirqd_routing;
uint8_t pirqe_routing;
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
/**
* Device Interrupt Routing configuration
* Interrupt Pin x Route.
* 0h = PIRQA#
* 1h = PIRQB#
* 2h = PIRQC#
* 3h = PIRQD#
* 4h = PIRQE#
* 5h = PIRQF#
* 6h = PIRQG#
* 7h = PIRQH#
*/
uint16_t ir00_routing;
uint16_t ir01_routing;
uint16_t ir02_routing;
uint16_t ir03_routing;
uint16_t ir04_routing;
/**
* Device Interrupt Polarity Control
* ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
* ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
* ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
* ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
*/
uint32_t ipc0;
uint32_t ipc1;
uint32_t ipc2;
uint32_t ipc3;
uint64_t turbo_ratio_limit;
uint64_t turbo_ratio_limit_cores;
uint32_t pstate_req_ratio;
uint32_t vtd_support;
uint32_t coherency_support;
uint32_t ats_support;
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;
uint32_t gen3_dec;
uint32_t gen4_dec;
/* TCC activation offset */
uint32_t tcc_offset;
};
typedef struct soc_intel_xeon_sp_skx_config config_t;
#endif
|
