1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <build.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <soc/bootblock.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/lpc.h>
#include <soc/pm.h>
#include <soc/spi.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp, NULL, 0);
}
static void program_base_addresses(void)
{
uint32_t reg;
const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
/* Memory Mapped IO registers. */
reg = PMC_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PBASE, reg);
reg = IO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IOBASE, reg);
reg = ILB_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IBASE, reg);
reg = SPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, SBASE, reg);
reg = MPHY_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, MPBASE, reg);
reg = PUNIT_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PUBASE, reg);
reg = RCBA_BASE_ADDRESS | 1;
pci_write_config32(lpc_dev, RCBA, reg);
/* IO Port Registers. */
reg = ACPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, ABASE, reg);
reg = GPIO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, GBASE, reg);
}
static void tco_disable(void)
{
uint32_t reg;
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
reg |= TCO_TMR_HALT;
outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
}
static void spi_init(void)
{
void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
write32(scs, read32(scs) & ~SMIWPEN);
/*
* Enable caching and prefetching in the SPI controller. Disable
* the SMM-only BIOS write and set WPD bit.
*/
reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
reg &= ~EISS;
write32(bcr, reg);
}
static void soc_rtc_init(void)
{
int rtc_failed = rtc_failure();
if (rtc_failed) {
printk(BIOS_ERR,
"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
COREBOOT_BUILD_MONTH_BCD,
COREBOOT_BUILD_DAY_BCD,
0x20,
COREBOOT_BUILD_YEAR_BCD);
}
cmos_init(rtc_failed);
}
static void setup_mmconfig(void)
{
uint32_t reg;
/*
* Set up the MMCONF range. The register lives in the BUNIT. The
* IO variant of the config access needs to be used initially to
* properly configure as the IOSF access registers live in PCI
* config space.
*/
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
}
void bootblock_soc_early_init(void)
{
/* Allow memory-mapped PCI config access. */
setup_mmconfig();
/* Early chipset initialization */
program_base_addresses();
tco_disable();
}
void bootblock_soc_init(void)
{
/* Continue chipset initialization */
soc_rtc_init();
set_max_freq();
spi_init();
lpc_init();
}
|
