1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <bootstate.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/pci_clk_req.h>
#include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/acpi.h>
#include <amdblocks/gpio.h>
#include <amdblocks/i2c.h>
#include <amdblocks/smi.h>
#include <soc/cpu.h>
#include <soc/i2c.h>
#include <soc/iomap.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>
#include <soc/pci_devs.h>
#include <static.h>
#include <types.h>
#include "chip.h"
/*
* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
* provides a visible association with the index, therefore helping
* maintainability of table. If a new index/name is defined in
* amd_pci_int_defs.h, just add the pair at the end of this table.
* Order is not important.
*/
static const struct irq_idx_name irq_association[] = {
{ PIRQ_A, "INTA#" },
{ PIRQ_B, "INTB#" },
{ PIRQ_C, "INTC#" },
{ PIRQ_D, "INTD#" },
{ PIRQ_E, "INTE#" },
{ PIRQ_F, "INTF#/GENINT2" },
{ PIRQ_G, "INTG#" },
{ PIRQ_H, "INTH#" },
{ PIRQ_MISC, "Misc" },
{ PIRQ_MISC0, "Misc0" },
{ PIRQ_MISC1, "Misc1" },
{ PIRQ_MISC2, "Misc2" },
{ PIRQ_SIRQA, "Ser IRQ INTA" },
{ PIRQ_SIRQB, "Ser IRQ INTB" },
{ PIRQ_SIRQC, "Ser IRQ INTC" },
{ PIRQ_SIRQD, "Ser IRQ INTD" },
{ PIRQ_SCI, "SCI" },
{ PIRQ_SMBUS, "SMBUS" },
{ PIRQ_ASF, "ASF" },
{ PIRQ_PMON, "PerMon" },
{ PIRQ_SD, "SD" },
{ PIRQ_SDIO, "SDIO" },
{ PIRQ_CIR, "CIR" },
{ PIRQ_GPIOA, "GPIOa" },
{ PIRQ_GPIOB, "GPIOb" },
{ PIRQ_GPIOC, "GPIOc" },
{ PIRQ_SATA, "SATA" },
{ PIRQ_EMMC, "eMMC" },
{ PIRQ_GPP0, "GPP0" },
{ PIRQ_GPP1, "GPP1" },
{ PIRQ_GPP2, "GPP2" },
{ PIRQ_GPP3, "GPP3" },
{ PIRQ_GPIO, "GPIO" },
{ PIRQ_I2C0, "I2C0" },
{ PIRQ_I2C1, "I2C1" },
{ PIRQ_I2C2, "I2C2" },
{ PIRQ_I2C3, "I2C3" },
{ PIRQ_UART0, "UART0" },
{ PIRQ_UART1, "UART1" },
{ PIRQ_I2C4, "I2C4" },
{ PIRQ_I2C5, "I2C5" },
{ PIRQ_UART2, "UART2" },
{ PIRQ_UART3, "UART3" },
};
const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
{
*size = ARRAY_SIZE(irq_association);
return irq_association;
}
static void fch_clk_output_48Mhz(void)
{
u32 ctrl;
const struct soc_amd_picasso_config *cfg = config_of_soc();
ctrl = misc_read32(MISC_CLK_CNTL1);
/* If used external clock source for I2S, disable the internal clock output */
if (cfg->acp_i2s_use_external_48mhz_osc &&
cfg->common_config.acp_config.acp_pin_cfg == I2S_PINS_I2S_TDM)
ctrl &= ~BP_X48M0_OUTPUT_EN;
else
ctrl |= BP_X48M0_OUTPUT_EN;
misc_write32(MISC_CLK_CNTL1, ctrl);
}
static void sb_rfmux_config_override(void)
{
u8 port;
const struct soc_amd_picasso_config *cfg;
cfg = config_of_soc();
for (port = 0; port < USB_PD_PORT_COUNT; port++) {
if (cfg->usb_pd_config_override[port].rfmux_override_en) {
write32p(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port),
cfg->usb_pd_config_override[port].rfmux_config
| USB_PD_RFMUX_OVERRIDE);
}
}
}
static void fch_init_acpi_ports(void)
{
u32 reg;
/* We use some of these ports in SMM regardless of whether or not
* ACPI tables are generated. Enable these ports indiscriminately.
*/
pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */
pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
/* SMI on SlpTyp requires sending SMI before completion
response of the I/O write. */
reg = pm_read32(PM_PCI_CTRL);
reg |= FORCE_SLPSTATE_RETRY;
pm_write32(PM_PCI_CTRL, reg);
/* Disable SlpTyp feature */
reg = pm_read8(PM_RST_CTRL1);
reg &= ~SLPTYPE_CONTROL_EN;
pm_write8(PM_RST_CTRL1, reg);
configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
} else {
pm_write16(PM_ACPI_SMI_CMD, 0);
}
/* Decode ACPI registers and enable standard features */
pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
PM_ACPI_GLOBAL_EN |
PM_ACPI_RTC_EN_EN |
PM_ACPI_TIMER_EN_EN);
}
/*
* A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks
* and unneeded for Raven/Picasso so gate them to save power.
*/
static void al2ahb_clock_gate(void)
{
uint8_t al2ahb_val;
uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET);
al2ahb_val |= AL2AHB_CLK_GATE_EN;
write8p(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET, al2ahb_val);
al2ahb_val = read8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET);
al2ahb_val |= AL2AHB_HCLK_GATE_EN;
write8p(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET, al2ahb_val);
}
/* configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void)
{
struct soc_amd_picasso_config *cfg = config_of_soc();
gpp_clk_setup_common(&cfg->gpp_clk_config[0], ARRAY_SIZE(cfg->gpp_clk_config));
}
void fch_init(void *chip_info)
{
i2c_soc_init();
fch_init_acpi_ports();
acpi_pm_gpe_add_events_print_events();
gpio_add_events();
al2ahb_clock_gate();
gpp_clk_setup();
fch_clk_output_48Mhz();
sb_rfmux_config_override();
}
void fch_final(void *chip_info)
{
}
/*
* Update the PCI devices with a valid IRQ number
* that is set in the mainboard PCI_IRQ structures.
*/
static void set_pci_irqs(void *unused)
{
/* Write PCI_INTR regs 0xC00/0xC01 */
write_pci_int_table();
/* pirq_data is consumed by `write_pci_cfg_irqs` */
populate_pirq_data();
/* Write IRQs for all devicetree enabled devices */
write_pci_cfg_irqs();
}
/*
* Hook this function into the PCI state machine
* on entry into BS_DEV_ENABLE.
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);
|
