blob: 64ce4d82d9d36e8ac844e39c9f196a22584f5b46 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_INTEL_SANDYBRIDGE
bool
select CACHE_MRC_SETTINGS
select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
if NORTHBRIDGE_INTEL_SANDYBRIDGE
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config USE_NATIVE_RAMINIT
bool "Use native raminit"
default y
help
Select if you want to use coreboot implementation of raminit rather than
System Agent/MRC.bin. You should answer Y.
config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
default n
depends on USE_NATIVE_RAMINIT
help
Ignore the mainboard's vendor programmed fuses that might limit the
maximum DRAM frequency. By selecting this option the fuses will be
ignored and the only limits on DRAM frequency are set by RAM's SPD and
hard fuses in southbridge's clockgen.
Disabled by default as it might causes system instability.
Handle with care!
config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
bool "Ignore XMP profile max DIMMs per channel"
default n
depends on USE_NATIVE_RAMINIT
help
Ignore the max DIMMs per channel restriciton defined in XMP profiles.
Disabled by default as it might cause system instability.
Handle with care!
config CBFS_SIZE
hex
default 0x100000
config VGA_BIOS_ID
string
default "8086,0106"
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/sandybridge/bootblock.c"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
help
The MRC blob requires it to be at 0xf0000000.
config DCACHE_RAM_BASE
hex
default 0xfefe0000
if USE_NATIVE_RAMINIT
config DCACHE_RAM_SIZE
hex
default 0x20000
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x0
endif # USE_NATIVE_RAMINIT
if !USE_NATIVE_RAMINIT
config DCACHE_RAM_SIZE
hex
default 0x17000
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x9000
config MRC_FILE
string "Intel System Agent path and filename"
default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
binary.
endif # !USE_NATIVE_RAMINIT
endif
|
