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##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Google Inc.
## Copyright (C) 2013 Sage Electronic Engineering, LLC.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_206AX
config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
bool
select CPU_INTEL_FSP_MODEL_306AX
if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
config HAVE_FSP_BIN
bool "Use Intel Firmware Support Package"
help
Select this option to add an Intel FSP binary to
the resulting coreboot image.
Note: Without this binary, coreboot builds relying on the FSP
will not boot
config VGA_BIOS_ID
string
default "8086,0106"
help
This is the default PCI ID for the sandybridge/ivybridge graphics
devices. This string names the vbios rom in cbfs. The following
PCI IDs will be remapped to load this rom:
0x80860102, 0x8086010a, 0x80860112, 0x80860116
0x80860122, 0x80860126, 0x80860166
config DCACHE_RAM_BASE
hex
default 0xff7f0000
config DCACHE_RAM_SIZE
hex
default 0x10000
if HAVE_FSP_BIN
config FSP_FILE
string "Intel FSP binary path and filename"
default "../intel/fsp/ivybridge_bd82x6x/FvFsp.bin" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
default "../intel/fsp/ivybridge_i89xx/FvFsp.bin" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
help
The path and filename of the Intel FSP binary for this platform.
config FSP_LOC
hex "Intel FSP Binary location in cbfs"
default 0xfff80000
help
The location in cbfs that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with the Intel's BCT (tool).
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
default 0x100000
help
On Sandybridge and Ivybridge systems the firmware image may
have to store a lot more than just coreboot, including:
- a firmware descriptor
- Intel Management Engine firmware
This option specifies the maximum size of the CBFS portion in the
firmware image.
config ENABLE_FAST_BOOT
bool "Enable Fast Boot"
default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
help
Enabling this feature will cause MRC data to be cached in NV storage
which will speed up boot time on future reboots and/or power cycles.
config MRC_CACHE_SIZE
hex "MRC Data Cache Size"
default 0x10000
depends on ENABLE_FAST_BOOT
help
This is the amount of space in NV storage that is reserved for MRC data
cache storage when using fast boot.
config VIRTUAL_ROM_SIZE
hex "Virtual ROM Size"
default ROM_SIZE
depends on ENABLE_FAST_BOOT
help
This is used to calculate the offset of the MRC data cache in NV
Storage for "Fast Boot". If in doubt, leave this set to the default
which sets the virtual size equal to the ROM size.
Example: Cougar Canyon 2 has 2 8 MB SPI ROMs. When the SPI ROMs are
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.
endif # HAVE_FSP_BIN
endif # NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE
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