1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
|
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/cannonlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
register "power_limits_config" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 160,
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
}"
# Misc
register "AcousticNoiseMitigation" = "1"
# Power
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
# Thermal
register "tcc_offset" = "13"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "PMC_GPP_K"
register "gpe0_dw1" = "PMC_GPP_G"
register "gpe0_dw2" = "PMC_GPP_E"
# Actual device tree
device domain 0 on
subsystemid 0x1558 0x7714 inherit
device ref peg0 on
# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
register "PcieClkSrcUsage[7]" = "0x40"
register "PcieClkSrcClkReq[7]" = "7"
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
device ref dptf on end
device ref thermal on end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */
[1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */
[2] = USB2_PORT_MID(OC_SKIP), /* USB 3_4 */
[3] = USB2_PORT_MID(OC_SKIP), /* USB 3_3 */
[4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
[5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C */
[6] = USB2_PORT_MID(OC_SKIP), /* XFI */
[7] = USB2_PORT_MID(OC_SKIP), /* Camera */
[8] = USB2_PORT_MID(OC_SKIP), /* Light guide */
[9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
[13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_2 */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* ANX7440 */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_4 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */
}"
end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end
device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
device ref sata on
register "SataPortsEnable" = "{
[1] = 1, /* SATA1A (SSD) */
[3] = 1, /* SATA3 (M.2_SATA3) */
[4] = 1, /* SATA4 (SSD2) */
}"
end
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 14 (SSD2)
register "PcieRpEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieClkSrcUsage[14]" = "16"
register "PcieClkSrcClkReq[14]" = "14"
end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 15 (SSD3)
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[15]" = "20"
register "PcieClkSrcClkReq[15]" = "15"
end
device ref pcie_rp1 on
# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpHotPlug[0]" = "1"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
register "PcieClkSrcClkReq[6]" = "6"
end
device ref pcie_rp5 on
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[10]" = "4"
register "PcieClkSrcClkReq[10]" = "10"
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 8 (SSD)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[8]" = "8"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp13 on
# PCI Express root port #13 x1, Clock 0 (WLAN)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[0]" = "12"
register "PcieClkSrcClkReq[0]" = "0"
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 1 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[1]" = "13"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 4 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[4]" = "14"
register "PcieClkSrcClkReq[4]" = "4"
end
device ref lpc_espi on
register "gen1_dec" = "0x00040069"
register "gen2_dec" = "0x00fc0e01"
register "gen3_dec" = "0x00fc0f01"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
device ref smbus on end
end
end
|
