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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/intel/i945
# IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gpu_hotplug" = "0x00000220"
register "gpu_lvds_use_spread_spectrum_clock" = "1"
register "pwm_freq" = "275"
register "gpu_panel_power_up_delay" = "250"
register "gpu_panel_power_backlight_on_delay" = "2380"
register "gpu_panel_power_down_delay" = "250"
register "gpu_panel_power_backlight_off_delay" = "2380"
register "gpu_panel_power_cycle_delay" = "2"
device cpu_cluster 0 on
chip cpu/intel/socket_m
device lapic 0 on end
end
end
register "pci_mmio_size" = "768"
device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2017
end
device pci 01.0 on # PEG
device pci 00.0 on end # VGA
end
device pci 02.0 on # GMA Graphics controller
subsystemid 0x17aa 0x201a
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0b"
register "pirqb_routing" = "0x0b"
register "pirqc_routing" = "0x0b"
register "pirqd_routing" = "0x0b"
register "pirqe_routing" = "0x0b"
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "2"
register "gpi12_routing" = "2"
register "gpi8_routing" = "2"
register "sata_ports_implemented" = "0x01"
register "gpe0_en" = "0x11000006"
register "alt_gp_smi_en" = "0x1000"
register "c4onc3_enable" = "1"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
subsystemid 0x17aa 0x2010
end
device pci 1c.0 on # PCI Express Port 1
subsystemid 0x17aa 0x2011
end
device pci 1c.1 on # PCI Express Port 2
subsystemid 0x17aa 0x2011
end
device pci 1c.2 on # PCI Express Port 3
subsystemid 0x17aa 0x2011
end
device pci 1c.3 on # PCI Express Port 4
subsystemid 0x17aa 0x2011
end
device pci 1c.4 off end # PCIe port 5
device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.1 on # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.2 on # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.3 on # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.7 on # USB2 EHCI
subsystemid 0x17aa 0x200b
end
device pci 1e.0 on # PCI Bridge
chip southbridge/ti/pci1x2x
device pci 00.0 on
subsystemid 0x17aa 0x2013
end
register "scr" = "0x0844d070"
register "mrr" = "0x01d01002"
end
end
device pci 1e.2 off end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
end
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
register "config0" = "0xa6"
register "config1" = "0x05"
register "config2" = "0xa0"
register "config3" = "0x01"
register "beepmask0" = "0xfe"
register "beepmask1" = "0x96"
register "has_power_management_beeps" = "1"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xf4"
register "event5_enable" = "0x3f"
register "event6_enable" = "0x80"
register "event7_enable" = "0x01"
register "event8_enable" = "0x01"
register "event9_enable" = "0xff"
register "eventa_enable" = "0xff"
register "eventb_enable" = "0xff"
register "eventc_enable" = "0x3c"
register "eventd_enable" = "0xff"
end
chip superio/nsc/pc87382
device pnp 164e.2 on # IR
io 0x60 = 0x2f8
end
device pnp 164e.3 off # Serial Port
io 0x60 = 0x3f8
end
device pnp 164e.7 on # GPIO
io 0x60 = 0x1680
end
device pnp 164e.19 on # DLPC
io 0x60 = 0x164c
end
end
chip superio/nsc/pc87384
device pnp 2e.0 off #FDC
end
device pnp 2e.1 on # Parallel Port
io 0x60 = 0x3bc
irq 0x70 = 7
end
device pnp 2e.2 off # Serial Port / IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Serial Port
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x1620
end
device pnp 2e.a off # WDT
end
end
end
device pci 1f.2 on # SATA
subsystemid 0x17aa 0x200d
end
device pci 1f.3 on # SMBUS
subsystemid 0x17aa 0x200f
chip drivers/i2c/ck505
register "mask" = "{ 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff }"
# vendor clockgen setup
register "regs" = "{ 0x6d, 0xff, 0xff,
0x20, 0x41, 0x7f, 0x18, 0x00 }"
device i2c 69 on end
end
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
device i2c 55 on end
device i2c 56 on end
device i2c 57 on end
device i2c 5c on end
device i2c 5d on end
device i2c 5e on end
device i2c 5f on end
end
end
end
end
end
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