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|
chip soc/intel/apollolake
device cpu_cluster 0 on
device lapic 0 on end
end
register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# Set de-emphasis to disabled for PCIE WiFI (Thunderpeak)
# as it is required for detection
register "pcie_rp_deemphasis_enable[2]" = "0"
# Set de-emphasis to default (enabled) for remaining ports
register "pcie_rp_deemphasis_enable[0]" = "1"
register "pcie_rp_deemphasis_enable[1]" = "1"
register "pcie_rp_deemphasis_enable[3]" = "1"
register "pcie_rp_deemphasis_enable[4]" = "1"
register "pcie_rp_deemphasis_enable[5]" = "1"
# GPIO for PERST_0 (WLAN_PE_RST)
register "prt0_gpio" = "GPIO_164"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
# DW1 is used by:
# - GPIO_63 - H1_PCH_INT_ODL
# DW2 is used by:
# - GPIO_141 - EC_PCH_WAKE_ODL
# - GPIO_142 - TRACKPAD_INT2_1V8_ODL
# - GPIO_144 - PEN_EJECT_ODL
# DW3 is used by:
# - GPIO_117 - LTE_WAKE_ODL
# - GPIO_119 - WLAN_PCIE_WAKE_ODL
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_N_63_32"
# PL1 override 10000 mW: Due to error in the energy calculation for
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 10W.
register "tdp_pl1_override_mw" = "10000"
# Set RAPL PL2 to 15W.
register "tdp_pl2_override_mw" = "15000"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C0 | Digitizer |
#| I2C5 | Audio |
#| I2C6 | Trackpad |
#| I2C7 | Touchscreen |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[6] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[7] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
}"
register "pnp_settings" = "PNP_PERF_POWER"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
device pci 00.2 off end # - NPK
device pci 02.0 on end # - Gen
device pci 03.0 on end # - Iunit
chip drivers/intel/wifi
register "wake" = "GPE0A_CNVI_PME_STS"
device pci 0c.0 on end # - CNVi
end
device pci 0d.0 on end # - P2SB
device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - Fast SPI
device pci 0d.3 on end # - Shared SRAM
device pci 0e.0 on
chip drivers/generic/max98357a
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end # - Audio
device pci 0f.0 on end # - Heci1
device pci 0f.1 on end # - Heci2
device pci 0f.2 on end # - Heci3
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW3_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)
device pci 13.1 off end # - PCIe-A 1
device pci 13.2 off end # - PCIe-A 2
device pci 13.3 off end # - PCIe-A 3
device pci 14.0 off end # - PCIe-B 0
device pci 14.1 off end # - PCIe-B 1
device pci 15.0 on end # - XHCI
device pci 15.1 on end # - XDCI
device pci 16.0 on end # - I2C 0
device pci 16.1 on end # - I2C 1
device pci 16.2 off end # - I2C 2
device pci 16.3 off end # - I2C 3
device pci 17.0 on end # - I2C 4
device pci 17.1 on end # - I2C 5
device pci 17.2 on end # - I2C 6
device pci 17.3 off end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2
device pci 18.3 off end # - UART 3
device pci 19.0 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_63_IRQ)"
device spi 0 on end
end
end # - GSPI 0
device pci 19.1 off end # - SPI 1
device pci 19.2 on end # - SPI 2
device pci 1a.0 on end # - PWM
device pci 1c.0 on end # - eMMC
device pci 1e.0 off end # - SDIO
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # - ESPI
device pci 1f.1 on end # - SMBUS
end
end
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