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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 AMD
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
default CONFIG_ROM_PAYLOAD = 1
arch i386 end
driver mainboard.o
if HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
depends "$(MAINBOARD)/dsdt.asl"
action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
end
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
mainboardinit southbridge/via/k8t890/romstrap.inc
ldscript /southbridge/via/k8t890/romstrap.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
mainboardinit cpu/amd/car/cache_as_ram.inc
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
chip cpu/amd/socket_939 # CPU
device apic 0 on end # APIC
end
end
device pci_domain 0 on # PCI domain
chip northbridge/amd/amdk8 # mc0
device pci 18.0 on # Northbridge
# Devices on link 0, link 0 == LDT 0
chip southbridge/via/vt8237r # Southbridge
register "ide0_enable" = "1" # Enable IDE channel 0
register "ide1_enable" = "1" # Enable IDE channel 1
register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
register "fn_ctrl_lo" = "0" # Enable SB functions
register "fn_ctrl_hi" = "0xad" # Enable SB functions
device pci 0.0 on end # HT
device pci f.1 on end # IDE
device pci 11.0 on # LPC
chip drivers/generic/generic # DIMM 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic # DIMM 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic # DIMM 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic # DIMM 0-1-1
device i2c 53 on end
end
chip superio/winbond/w83627ehg # Super I/O
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2 (N/A on this board)
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 off # PS/2 keyboard (off)
end
device pnp 2e.106 off # Serial flash
io 0x60 = 0x100
end
device pnp 2e.007 off # GPIO 1
end
device pnp 2e.107 on # Game port
io 0x60 = 0x201
end
device pnp 2e.207 on # MIDI
io 0x62 = 0x330
irq 0x70 = 0xa
end
device pnp 2e.307 off # GPIO 6
end
device pnp 2e.8 off # WDTO_PLED
end
device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
end
device pnp 2e.109 off # GPIO 3
end
device pnp 2e.209 off # GPIO 4
end
device pnp 2e.309 on # GPIO5
end
device pnp 2e.a off # ACPI
end
device pnp 2e.b on # Hardware monitor
io 0x60 = 0x290
irq 0x70 = 0
end
end
end
device pci 12.0 off end # VIA LAN (off, other chip used)
end
chip southbridge/via/k8t890 # "Southbridge" K8T890
end
end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
end
end
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