/** @file
Copyright (c) 2019, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#include
#pragma pack(1)
///
/// Azalia Header structure
///
typedef struct {
UINT16 VendorId; ///< Codec Vendor ID
UINT16 DeviceId; ///< Codec Device ID
UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
} AZALIA_HEADER;
///
/// Audio Azalia Verb Table structure
///
typedef struct {
AZALIA_HEADER Header; ///< AZALIA PCH header
UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
} AUDIO_AZALIA_VERB_TABLE;
///
/// Refer to the definition of PCH_INT_PIN
///
typedef enum {
SiPchNoInt, ///< No Interrupt Pin
SiPchIntA,
SiPchIntB,
SiPchIntC,
SiPchIntD
} SI_PCH_INT_PIN;
///
/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
///
typedef struct {
UINT8 Device; ///< Device number
UINT8 Function; ///< Device function
UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
UINT8 Irq; ///< IRQ to be set for device.
} SI_PCH_DEVICE_INTERRUPT_CONFIG;
#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
/** Fsp S Configuration
**/
typedef struct {
/** Offset 0x0020 - Reserved
**/
UINT8 Reserved0[16];
/** Offset 0x0030 - Graphics Configuration Ptr
Points to VBT
**/
UINT32 GraphicsConfigPtr;
/** Offset 0x0034 - Enable Device 4
Enable/disable Device 4
$EN_DIS
**/
UINT8 Device4Enable;
/** Offset 0x0035 - Enable eMMC Controller
Enable/disable eMMC Controller.
$EN_DIS
**/
UINT8 ScsEmmcEnabled;
/** Offset 0x0036 - Enable eMMC HS400 Mode
Enable eMMC HS400 Mode.
$EN_DIS
**/
UINT8 ScsEmmcHs400Enabled;
/** Offset 0x0037 - Use DLL values from policy
Set if FSP should use HS400 DLL values from policy
$EN_DIS
**/
UINT8 EmmcUseCustomDlls;
/** Offset 0x0038 - Emmc Tx CMD Delay control register value
Please see Tx CMD Delay Control register definition for help
**/
UINT32 EmmcTxCmdDelayRegValue;
/** Offset 0x003C - Emmc Tx DATA Delay control 1 register value
Please see Tx DATA Delay control 1 register definition for help
**/
UINT32 EmmcTxDataDelay1RegValue;
/** Offset 0x0040 - Emmc Tx DATA Delay control 2 register value
Please see Tx DATA Delay control 2 register definition for help
**/
UINT32 EmmcTxDataDelay2RegValue;
/** Offset 0x0044 - Emmc Rx CMD + DATA Delay control 1 register value
Please see Rx CMD + DATA Delay control 1 register definition for help
**/
UINT32 EmmcRxCmdDataDelay1RegValue;
/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 2 register value
Please see Rx CMD + DATA Delay control 2 register definition for help
**/
UINT32 EmmcRxCmdDataDelay2RegValue;
/** Offset 0x004C - Emmc Rx Strobe Delay control register value
Please see Rx Strobe Delay control register definition for help
**/
UINT32 EmmcRxStrobeDelayRegValue;
/** Offset 0x0050 - Enable SdCard Controller
Enable/disable SD Card Controller.
$EN_DIS
**/
UINT8 ScsSdCardEnabled;
/** Offset 0x0051 - SdCard power enable polarity
Choose SD_PWREN# polarity
0: Active low, 1: Active high
**/
UINT8 SdCardPowerEnableActiveHigh;
/** Offset 0x0052 - Reserved
**/
UINT8 Reserved1[34];
/** Offset 0x0074 - SdCard Command Pad Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up
**/
UINT8 SdCardGpioCmdPadTermination;
/** Offset 0x0075 - Reserved
**/
UINT8 Reserved2[136];
/** Offset 0x00FD - Enable SATA SALP Support
Enable/disable SATA Aggressive Link Power Management.
$EN_DIS
**/
UINT8 SataSalpSupport;
/** Offset 0x00FE - Enable SATA ports
Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
and so on.
**/
UINT8 SataPortsEnable[8];
/** Offset 0x0106 - Enable SATA DEVSLP Feature
Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlp[8];
/** Offset 0x010E - Enable USB2 ports
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb20Enable[16];
/** Offset 0x011E - Enable USB3 ports
Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
port1, and so on.
**/
UINT8 PortUsb30Enable[10];
/** Offset 0x0128 - Enable xDCI controller
Enable/disable to xDCI controller.
$EN_DIS
**/
UINT8 XdciEnable;
/** Offset 0x0129 - Reserved
**/
UINT8 Reserved3[28];
/** Offset 0x0145 - Enable SATA
Enable/disable SATA controller.
$EN_DIS
**/
UINT8 SataEnable;
/** Offset 0x0146 - SATA Mode
Select SATA controller working mode.
0:AHCI, 1:RAID
**/
UINT8 SataMode;
/** Offset 0x0147 - SPIn Device Mode
Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
**/
UINT8 SerialIoSpiMode[7];
/** Offset 0x014E - SPI Chip Select Polarity
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
1:SerialIoSpiCsActiveHigh
**/
UINT8 SerialIoSpiCsPolarity[14];
/** Offset 0x015C - Reserved
**/
UINT8 Reserved4[21];
/** Offset 0x0171 - SPIn Default Chip Select Mode HW/SW
Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
SPI1, ... Available options: 0:HW, 1:SW
**/
UINT8 SerialIoSpiCsMode[7];
/** Offset 0x0178 - SPIn Default Chip Select State Low/High
Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
Available options: 0:Low, 1:High
**/
UINT8 SerialIoSpiCsState[7];
/** Offset 0x017F - UARTn Device Mode
Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartMode[7];
/** Offset 0x0186 - Reserved
**/
UINT8 Reserved5[186];
/** Offset 0x0240 - UART Number For Debug Purpose
UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
for debug purpose.
0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
**/
UINT8 SerialIoDebugUartNumber;
/** Offset 0x0241 - Reserved
**/
UINT8 Reserved6[7];
/** Offset 0x0248 - I2Cn Device Mode
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
**/
UINT8 SerialIoI2cMode[8];
/** Offset 0x0250 - Reserved
**/
UINT8 Reserved7[72];
/** Offset 0x0298 - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
**/
UINT8 Usb2PhyPetxiset[16];
/** Offset 0x02A8 - USB Per Port HS Transmitter Bias
USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
**/
UINT8 Usb2PhyTxiset[16];
/** Offset 0x02B8 - USB Per Port HS Transmitter Emphasis
USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
**/
UINT8 Usb2PhyPredeemp[16];
/** Offset 0x02C8 - USB Per Port Half Bit Pre-emphasis
USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
One byte for each port.
**/
UINT8 Usb2PhyPehalfbit[16];
/** Offset 0x02D8 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDeEmphEnable[10];
/** Offset 0x02E2 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port.
**/
UINT8 Usb3HsioTxDeEmph[10];
/** Offset 0x02EC - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmpEnable[10];
/** Offset 0x02F6 - USB 3.0 TX Output Downscale Amplitude Adjustment
USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default
= 00h. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmp[10];
/** Offset 0x0300 - Enable LAN
Enable/disable LAN controller.
$EN_DIS
**/
UINT8 PchLanEnable;
/** Offset 0x0301 - Reserved
**/
UINT8 Reserved8[83];
/** Offset 0x0354 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtV1p05RailVoltage;
/** Offset 0x0356 - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtV1p05RailIccMax;
/** Offset 0x0357 - Reserved
**/
UINT8 Reserved9;
/** Offset 0x0358 - External Vnn Voltage Value that will be used in S0ix/Sx states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtVnnRailVoltage;
/** Offset 0x035A - External Vnn Icc Max Value that will be used in S0ix/Sx states
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailIccMax;
/** Offset 0x035B - Reserved
**/
UINT8 Reserved10;
/** Offset 0x035C - External Vnn Voltage Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
(0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtVnnRailSxVoltage;
/** Offset 0x035E - External Vnn Icc Max Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailSxIccMax;
/** Offset 0x035F - Reserved
**/
UINT8 Reserved11[3];
/** Offset 0x0362 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
**/
UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
/** Offset 0x0364 - Reserved
**/
UINT8 Reserved12[22];
/** Offset 0x037A - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
/** Offset 0x037B - Reserved
**/
UINT8 Reserved13;
/** Offset 0x037C - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. ICP-N: GPP_H12 = 0x2746E40C(default)
or GPP_H1 = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
/** Offset 0x0380 - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. ICP-N: GPP_H13 = 0x2746E60D(default)
or GPP_H2 = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
/** Offset 0x0384 - Reserved
**/
UINT8 Reserved14[6];
/** Offset 0x038A - HECI3 state
The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
0: disable, 1: enable
$EN_DIS
**/
UINT8 Heci3Enabled;
/** Offset 0x038B - Reserved
**/
UINT8 Reserved15[141];
/** Offset 0x0418 - CdClock Frequency selection
0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180
Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz,
9: 652.8 Mhz
0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190
Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz
**/
UINT8 CdClock;
/** Offset 0x0419 - Enable/Disable PeiGraphicsPeimInit
Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
/** Offset 0x041A - Reserved
**/
UINT8 Reserved16[160];
/** Offset 0x04BA - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
API. 0: Initialize; 1: Skip
$EN_DIS
**/
UINT8 SkipMpInit;
/** Offset 0x04BB - Reserved
**/
UINT8 Reserved17[9];
/** Offset 0x04C4 - CpuMpPpi
Pointer for CpuMpPpi
**/
UINT32 CpuMpPpi;
/** Offset 0x04C8 - Reserved
**/
UINT8 Reserved18[86];
/** Offset 0x051E - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
/** Offset 0x051F - Reserved
**/
UINT8 Reserved19[24];
/** Offset 0x0537 - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
**/
UINT8 PcieRpPmSci[24];
/** Offset 0x054F - Reserved
**/
UINT8 Reserved20[24];
/** Offset 0x0567 - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[24];
/** Offset 0x057F - Reserved
**/
UINT8 Reserved21[455];
/** Offset 0x0746 - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
/** Offset 0x0747 - Reserved
**/
UINT8 Reserved22;
/** Offset 0x0748 - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
/** Offset 0x0749 - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
/** Offset 0x074A - Reserved
**/
UINT8 Reserved23[11];
/** Offset 0x0755 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
/** Offset 0x0756 - Reserved
**/
UINT8 Reserved24[146];
/** Offset 0x07E8 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
/** Offset 0x07F8 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
/** Offset 0x0802 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
$EN_DIS
**/
UINT8 Enable8254ClockGating;
/** Offset 0x0803 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
$EN_DIS
**/
UINT8 Enable8254ClockGatingOnS3;
/** Offset 0x0804 - Reserved
**/
UINT8 Reserved25[531];
/** Offset 0x0A17 - Enable/Disable IGFX PmSupport
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
$EN_DIS
**/
UINT8 PmSupport;
/** Offset 0x0A18 - Reserved
**/
UINT8 Reserved26[32];
/** Offset 0x0A38 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
10, For all other SKUs the recommended default are 0
**/
UINT8 TccActivationOffset;
/** Offset 0x0A39 - Reserved
**/
UINT8 Reserved27[34];
/** Offset 0x0A5B - Enable or Disable CPU power states (C-states)
Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
$EN_DIS
**/
UINT8 Cx;
/** Offset 0x0A5C - Reserved
**/
UINT8 Reserved28[74];
/** Offset 0x0AA6 - Platform Power Pmax
PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments.
Range 0-1024 Watts. Value of 800 = 100W
**/
UINT16 PsysPmax;
/** Offset 0x0AA8 - Reserved
**/
UINT8 Reserved29[116];
/** Offset 0x0B1C - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
/** Offset 0x0B1D - Reserved
**/
UINT8 Reserved30[3];
/** Offset 0x0B20 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
/** Offset 0x0B21 - Reserved
**/
UINT8 Reserved31[447];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct {
/** Offset 0x0000
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
FSP_S_CONFIG FspsConfig;
/** Offset 0x0CE0
**/
UINT8 UnusedUpdSpace37[6];
/** Offset 0x0CE6
**/
UINT16 UpdTerminator;
} FSPS_UPD;
#pragma pack()
#endif