/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 314282 $ @e \$Date: 2015-03-08 04:44:40 -0500 (Sun, 08 Mar 2015) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _AGESA_H_
#define _AGESA_H_
#include "Porting.h"
#include "AMD.h"
//
//
// AGESA Types and Definitions
//
//
// AGESA BASIC CALLOUTS
#define AGESA_MEM_RELEASE 0x00028000ul
// AGESA ADVANCED CALLOUTS, Processor
#define AGESA_CHECK_UMA 0x00028100ul
#define AGESA_DO_RESET 0x00028101ul
#define AGESA_ALLOCATE_BUFFER 0x00028102ul
#define AGESA_DEALLOCATE_BUFFER 0x00028103ul
#define AGESA_LOCATE_BUFFER 0x00028104ul
#define AGESA_RUNFUNC_ONAP 0x00028105ul
#define AGESA_RUNFUNC_ON_ALL_APS 0x00028106ul
#define AGESA_IDLE_AN_AP 0x00028107ul
#define AGESA_WAIT_FOR_ALL_APS 0x00028108ul
// AGESA ADVANCED CALLOUTS, Memory
#define AGESA_READ_SPD 0x00028140ul
#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul
#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul
#define AGESA_READ_SPD_RECOVERY 0x00028143ul
#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul
#define AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE 0x00028146ul
#define AGESA_EXTERNAL_VOLTAGE_ADJUST 0x00028147ul
// AGESA IDS CALLOUTS
#define AGESA_GET_IDS_INIT_DATA 0x00028200ul
// AGESA GNB CALLOUTS
#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul
#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul
#define AGESA_GNB_PCIE_CLK_REQ 0x00028303ul
// AGESA FCH CALLOUTS
#define AGESA_FCH_OEM_CALLOUT 0x00028401ul
//-----------------------------------------------------------------------------
// FCH DEFINITIONS AND MACROS
//
//-----------------------------------------------------------------------------
/// Configuration values for SdConfig
typedef enum {
SdDisable = 0, ///< Disabled
SdVer2, ///< Version 2.0
SdVer3, ///< Version 3.0
SdV3SDR50, ///< V3 SdSDR50
SdV3SDR104, ///< V3 SdSDR104
SdV3DDR50, ///< V3 SdDDR50
SdDump ///< SD DUMP, don't touch SD
} SD_MODE;
/// Configuration values for SdClockControl
typedef enum {
Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default
Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz
Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz
} SD_CLOCK_CONTROL;
/// Configuration values for AzaliaController
typedef enum {
AzAuto = 0, ///< Auto - Detect Azalia controller automatically
AzDisable, ///< Diable - Disable Azalia controller
AzEnable ///< Enable - Enable Azalia controller
} HDA_CONFIG;
/// Configuration values for IrConfig
typedef enum {
IrDisable = 0, ///< Disable
IrRxTx0 = 1, ///< Rx and Tx0
IrRxTx1 = 2, ///< Rx and Tx1
IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1
} IR_CONFIG;
/// Configuration values for SataClass
typedef enum {
SataNativeIde = 0, ///< Native IDE mode
SataRaid, ///< RAID mode
SataAhci, ///< AHCI mode
SataLegacyIde, ///< Legacy IDE mode
SataIde2Ahci, ///< IDE->AHCI mode
SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver)
SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver)
} SATA_CLASS;
/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
typedef enum {
PortA4 = 0, ///< 4:0:0:0
PortA2B2 = 2, ///< 2:2:0:0
PortA2B1C1 = 3, ///< 2:1:1:0
PortA1B1C1D1 = 4 ///< 1:1:1:1
} GPP_LINKMODE;
/// Configuration values for FchPowerFail
typedef enum {
AlwaysOff = 0, ///< Always power off after power resumes
AlwaysOn = 1, ///< Always power on after power resumes
UsePrevious = 3, ///< Resume to same setting when power fails
} POWER_FAIL;
/// Configuration values for SATA Link Speed
typedef enum {
Gen1 = 1, ///< SATA port GEN1 speed
Gen2 = 2, ///< SATA port GEN2 speed
Gen3 = 3, ///< SATA port GEN3 speed
} SATA_SPEED;
/// Configuration values for GPIO function
typedef enum {
Function0 = 0, ///< GPIO Function 1
Function1 = 1, ///< GPIO Function 1
Function2 = 2, ///< GPIO Function 2
Function3 = 3, ///< GPIO Function 3
} GPIO_FUN;
/// Configuration values for memory phy voltage (VDDR)
#define VOLT0_95 0 ///< VDDR 0.95V
#define VOLT1_05 1 ///< VDDR 1.05V
#define MAX_VDDR 2 ///< Maxmum value for this enum definition
/// Configuration values for GPIO_CFG
typedef enum {
OwnedByEc = 1 << 0, ///< This bit can only be written by EC
OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS)
Sticky = 1 << 2, ///< If set, [6:3] are sticky
PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled
PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable
GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable
GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0
GpioIn = 1 << 7, ///< This bit is read only - current pin state
} CFG_BYTE;
/// Configuration values for GPIO_CFG2
typedef enum {
DrvStrengthSel_4mA = 0 << 1, ///< 18:17 DrvStrengthSel.
DrvStrengthSel_8mA = 1 << 1, ///< 18:17 DrvStrengthSel.
DrvStrengthSel_12mA = 2 << 1, ///< 18:17 DrvStrengthSel.
DrvStrengthSel_16mA = 3 << 1, ///< 18:17 DrvStrengthSel.
PullUpSel_8K = 1 << 3, ///< 19 PullUpSel. Read-write. 0=4 K pull-up is selected. 1=8 K pull-up is selected.
PullUpEnable = 1 << 4, ///< 20 PullUpEnable. Read-write. 0=Pull-up is disabled on the pin. 1=Pull-up is enabled on the pin.
PullDownEnable = 1 << 5, ///< 21 PullDownEnable. Read-write. 0=Pull-down is disabled on the pin. 1=Pull-down is enabled on thepin.
OutputValue = 1 << 6, ///< 22 OutputValue. Read-write. 0=low. 1=high.
OutputEnable = 1 << 7, ///< 23 OutputEnable. Read-write. 0=Output is disabled on the pin. 1=Output is enabled on the pin.
} CFG2_BYTE;
/// FCH GPIO CONTROL
typedef struct {
IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
IN GPIO_FUN PinFunction; ///< Multi-function selection
IN CFG_BYTE CfgByte; ///< GPIO Register value
} GPIO_CONTROL;
///
/// FCH SCI MAP CONTROL
///
typedef struct {
IN UINT8 InputPin; ///< Input Pin, valid range 0-63
IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31
} SCI_MAP_CONTROL;
///
/// FCH SATA PHY CONTROL
///
typedef struct {
IN BOOLEAN CommonPhy; ///< Common PHY or not
///< @li FALSE - Only applied to specified port
///< @li TRUE - Apply to all SATA ports
IN SATA_SPEED Gen; ///< SATA speed
IN UINT8 Port; ///< Port number, valid range: 0-7
IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF
} SATA_PHY_CONTROL;
///
/// FCH Component Data Structure in InitReset stage
///
typedef struct {
IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
///< @li FALSE - Disable Gen2
///< @li TRUE - Enable Gen2
IN BOOLEAN SataEnable; ///< SATA controller function
///< @li FALSE - SATA controller is disabled
///< @li TRUE - SATA controller is enabled
IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
///< @li FALSE - IDE controller is disabled
///< @li TRUE - IDE controller is enabled
IN BOOLEAN GppEnable; ///< Master switch of GPP function
///< @li FALSE - GPP disabled
///< @li TRUE - GPP enabled
IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function
///< @li FALSE - XHCI0 controller disabled
///< @li TRUE - XHCI0 controller enabled
IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function
///< @li FALSE - XHCI1 controller disabled
///< @li TRUE - XHCI1 controller enabled
} FCH_RESET_INTERFACE;
///
/// FCH Component Data Structure from InitEnv stage
///
typedef struct {
IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode
IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller
IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration
IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
///< @li FALSE - Disable Gen2
///< @li TRUE - Enable Gen2
IN SATA_CLASS SataClass; ///< SATA controller mode
IN BOOLEAN SataEnable; ///< SATA controller function
///< @li FALSE - SATA controller is disabled
///< @li TRUE - SATA controller is enabled
IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
///< @li FALSE - IDE controller is disabled
///< @li TRUE - IDE controller is enabled
IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller
///< @li FALSE - Legacy IDE mode
///< @li TRUE - Native IDE mode
IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function
///< @li FALSE - OHCI1 is disabled
///< @li TRUE - OHCI1 is enabled
IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function
///< @li FALSE - OHCI2 is disabled
///< @li TRUE - OHCI2 is enabled
IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function
///< @li FALSE - OHCI3 is disabled
///< @li TRUE - OHCI3 is enabled
IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function
///< @li FALSE - OHCI4 is disabled
///< @li TRUE - OHCI4 is enabled
IN BOOLEAN GppEnable; ///< Master switch of GPP function
///< @li FALSE - GPP disabled
///< @li TRUE - GPP enabled
IN POWER_FAIL FchPowerFail; ///< FCH power failure option
} FCH_INTERFACE;
/*----------------------------------------------------------------------------
* CPU Feature related info
*----------------------------------------------------------------------------
*/
/// Build Configuration values for BLDCFG_PLATFORM_CONNECTED_STANDBY_MODE
typedef enum {
ConnectedStandbyAuto = 0, ///< Auto
ConnectedStandbyDisabled = 1, ///< Disabled
MaxConnectedStandbyMode = 2 ///< Not a valid value, used for verifying input
} PLATFORM_CONNECTED_STANDBY_MODES;
/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
typedef enum {
CStateModeDisabled = 0, ///< Disabled
CStateModeC6 = 1, ///< C6 State
MaxCStateMode = 2 ///< Not a valid value, used for verifying input
} PLATFORM_CSTATE_MODES;
/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
typedef enum {
CpbModeAuto = 0, ///< Auto
CpbModeDisabled = 1, ///< Disabled
MaxCpbMode = 2 ///< Not a valid value, used for verifying input
} PLATFORM_CPB_MODES;
/// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
#define PsdPolicyProcessorDefault 0 ///< PSD is dependent or independent per processor default
#define PsdPolicyDependent 1 ///< PSD is forced dependent
#define PsdPolicyIndependent 2 ///< PSD is forced independent
#define PsdPolicyMax 3 ///< Not a valid value, used for verifying input
/*----------------------------------------------------------------------------
* GNB PCIe configuration info
*----------------------------------------------------------------------------
*/
// Event definitions
#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid
#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported
#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address
#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration
#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link
#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes
#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported
#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail
#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training
#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training
#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
#define DESCRIPTOR_IGNORE 0x40000000ull
/// PCIe link initialization
typedef enum {
EndpointDetect = 0, ///< Detect endpoint presence
EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine
///< if device present on board or in slot. For example GPIO can be used to determine device presence.
} PCIE_ENDPOINT_STATUS;
/// PCIe port misc extended controls
typedef struct {
IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
* @li @b 0 - port can advertize muximum supported capability
* @li @b 1 - port limit advertized capability and speed to PCIe Gen1
*/
IN UINT8 SbLink :1; /**< PCIe link type
* @li @b 0 - General purpose port
* @li @b 1 - Port connected to SB
*/
IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support
* @li @b 0 - Clock Power Management not configured
* @li @b 1 - Clock Power Management configured according to PCIe device capability
*/
} PCIe_PORT_MISC_CONTROL;
/// The IO APIC Interrupt Mapping Info
typedef struct {
IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
* @li 0 - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS
* @li 1 - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
* @li 2 - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
* @li ...
* @li 8 - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
*/
IN UINT8 Swizzle; /**< Swizzle interrupt in the Group.
* @li 0 - ABCD
* @li 1 - BCDA
* @li 2 - CDAB
* @li 3 - DABC
*/
IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt
* @li 0 - Entry 0 of IO APIC redirection table
* @li 1 - Entry 1 of IO APIC redirection table
* @li ...
* @li 31 - Entry 31 of IO APIC redirection table
*/
} APIC_DEVICE_INFO;
/// Initial Offset Calibration Control
typedef enum {
ADAPT_IOC_DISABLED = 0, ///< Initial Offset Calibration Disabled
ADAPT_IOC_ENABLED ///< Initial Offset Calibration Enabled
} ADAPT_IOC_CONTROL;
/// DFE Control values
typedef enum {
ADAPT_DFE_CONTROL_DISABLED = 0, ///< DFE Disabled
ADAPD_DFE_CONTROL_1TAP_DFE = 4, ///< 1-tap DFE
ADAPD_DFE_CONTROL_1TAP_DFE_FBF, ///< 1-tap DFE with Future Bit Filtering
ADAPD_DFE_CONTROL_2TAP_DFE, ///< 2-tap DFE
ADAPD_DFE_CONTROL_2TAP_DFE_FBF ///< 2-tap DFE with Future Bit Filtering
} ADAPT_DFE_CONTROL;
/// LEQ Control values
typedef enum {
ADAPT_LEQ_CONTROL_DISABLED = 0, ///< LEQ Disabled
ADAPT_LEQ_CONTROL_DC_GAIN = 2, ///< DC Gain Adaptation
ADAPT_LEQ_CONTROL_DC_GAIN_POLE ///< DC Gain and Pole Adaptation
} ADAPT_LEQ_CONTROL;
/// Dynamic Offset Calibration Control
typedef enum {
ADAPT_DOC_DISABLED = 0, ///< Dynamic Offset Calibration Disabled
ADAPT_DOC_ENABLED ///< Dynamic Offset Calibration Enabled
} ADAPT_DOC_CONTROL;
/// FOM Calculation Control
typedef enum {
ADAPT_FOMC_DISABLED = 0, ///< FOM Calculation Disabled
ADAPT_FOMC_ENABLED ///< FOM Calculation Enabled
} ADAPT_FOMC_CONTROL;
/// PI Offset Calibration Control
typedef enum {
ADAPT_PIOC_DISABLED = 0, ///< PI Offset Calibration Disabled
ADAPT_PIOC_ENABLED ///< PI Offset Calibration Enabled
} ADAPT_PIOC_CONTROL;
/// GEN3 RxAdaptMode Configuration Structure
typedef struct {
IN BOOLEAN InitOffsetCancellation; ///< Initial Offset Cancellation Enable
IN UINT8 DFEControl; ///< DFE Control
IN UINT8 LEQControl; ///< LEQ Control
IN BOOLEAN DynamicOffsetCalibration; ///< Dynamic Offset Calibration Enable
IN BOOLEAN FOMCalculation; ///< FOM Calculation Enable
IN BOOLEAN PIOffsetCalibration; ///< PI Offset Calibratino Enable
} RX_ADAPT_MODE;
/// PCIe port configuration data
typedef struct {
IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
IN UINT8 ChannelType; /**< Channel type.
* @li @b 0 - "lowLoss",
* @li @b 1 - "highLoss",
* @li @b 2 - "mob0db",
* @li @b 3 - "mob3db",
* @li @b 4 - "extnd6db"
* @li @b 5 - "extnd8db"
*/
IN UINT8 DeviceNumber; /**< PCI Device number for port.
* @li @b 0 - Native port device number
* @li @b N - Port device number (See available configurations in BKDG
*/
IN UINT8 FunctionNumber; ///< Reserved for future use
IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
* @li @b 0 - Maximum supported by silicon
* @li @b 1 - Gen1
* @li @b 2 - Gen2
* @li @b 3 - Gen3
*/
IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
* @li @b 0 - Disabled
* @li @b 1 - L0s only
* @li @b 2 - L1 only
* @li @b 3 - L0s and L1
*/
IN UINT8 LinkHotplug; /**< Hotplug control.
* @li @b 0 - Disabled
* @li @b 1 - Basic
* @li @b 2 - Server
* @li @b 3 - Enhanced
*/
IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
* identification which control reset for given port.
* Each port with unique GPIO should have unique ResetId assigned.
* All ports use same GPIO to control reset should have same ResetId assigned.
* see AgesaPcieSlotResetContol.
*/
IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info
IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status
IN RX_ADAPT_MODE RxAdaptMode; ///< Gen3 RxAdaptMode configuration
} PCIe_PORT_DATA;
/// DDI channel lane mapping
typedef struct { ///< Structure that discribe lane mapping
IN UINT8 Lane0 :2; /**< Lane 0 mapping
* @li @b 0 - Map to lane 0
* @li @b 1 - Map to lane 1
* @li @b 2 - Map to lane 2
* @li @b 2 - Map to lane 3
*/
IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
} CHANNEL_MAPPING; ///< Lane mapping
/// Common Channel Mapping
typedef union {
IN UINT8 ChannelMappingValue; ///< Raw lane mapping
IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
} CONN_CHANNEL_MAPPING;
/// DDI Configuration data
typedef struct {
IN UINT8 ConnectorType; /**< Display Connector Type
* @li @b 0 - DP
* @li @b 1 - eDP
* @li @b 2 - Single Link DVI-D
* @li @b 3 - Dual Link DVI-D (see @ref DualLinkDviDescription "Example Dual Link DVI connector description")
* @li @b 4 - HDMI
* @li @b 5 - DP-to-VGA
* @li @b 6 - DP-to-LVDS
* @li @b 7 - Hudson-2 NutMeg DP-to-VGA
* @li @b 8 - Single Link DVI-I
* @li @b 9 - Native CRT (Family 0x14)
* @li @b 10 - Native LVDS (Family 0x14)
* @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS
* The auto detection method only support panel with EDID.
*/
IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
* @li @b 0 - AUX1
* @li @b 1 - AUX2
* @li @b 2 - AUX3
* @li @b 3 - AUX4
* @li @b 4 - AUX5
* @li @b 5 - AUX6
*/
IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
* @li @b 0 - HDP1
* @li @b 1 - HDP2
* @li @b 2 - HDP3
* @li @b 3 - HDP4
* @li @b 4 - HDP5
* @li @b 5 - HDP6
*/
IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
* @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
* @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
* if Mapping[x] set to 0 than default mapping assumed
*/
IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
* @li 0 - Do not invert (default)
* @li 1 - Invert P and N on this lane
*/
IN UINT8 Flags; /**< Capabilities flags
* @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
* @li Flags bit[7:1] Reserved
*/
} PCIe_DDI_DATA;
/// Engine Configuration
typedef struct {
IN UINT8 EngineType; /**< Engine type
* @li @b 0 - Ignore engine configuration
* @li @b 1 - PCIe port
* @li @b 2 - DDI
*/
IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
* Refer to lane descriptions and supported configurations in BKDG
*/
IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
* Refer to lane descriptions and supported configurations in BKDG
*/
} PCIe_ENGINE_DATA;
/// PCIe port descriptor
typedef struct {
IN UINT32 Flags; /**< Descriptor flags
* @li @b Bit31 - last descriptor in complex
*/
IN PCIe_ENGINE_DATA EngineData; ///< Engine data
IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
} PCIe_PORT_DESCRIPTOR;
/// DDI descriptor
typedef struct {
IN UINT32 Flags; /**< Descriptor flags
* @li @b Bit31 - last descriptor in complex
*/
IN PCIe_ENGINE_DATA EngineData; ///< Engine data
IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
} PCIe_DDI_DESCRIPTOR;
/// PCIe Complex descriptor
typedef struct {
IN UINT32 Flags; /**< Descriptor flags
* @li @b Bit31 - last descriptor in topology
*/
IN UINT32 SocketId; ///< Socket Id
IN const PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
IN const PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
IN VOID *Reserved; ///< Reserved for future use
} PCIe_COMPLEX_DESCRIPTOR;
/// Action to control PCIe slot reset
typedef enum {
AssertSlotReset, ///< Assert slot reset
DeassertSlotReset ///< Deassert slot reset
} PCIE_RESET_CONTROL;
///Slot Reset Info
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
} PCIe_SLOT_RESET_INFO;
#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1
///VBIOS image info
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
OUT VOID *ImagePtr; ///< Pointer to VBIOS image
IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller
IN UINT32 Flags; ///< BIT[0] - special repost requred
} GFX_VBIOS_IMAGE_INFO;
/// Engine descriptor type
typedef enum {
PcieUnusedEngine = 0, ///< Unused descriptor
PciePortEngine = 1, ///< PCIe port
PcieDdiEngine = 2, ///< DDI
MaxPcieEngine ///< Max engine type for boundary check.
} PCIE_ENGINE_TYPE;
/// PCIe link capability/speed
typedef enum {
PcieGenMaxSupported, ///< Maximum supported
PcieGen1 = 1, ///< Gen1
PcieGen2, ///< Gen2
PcieGen3, ///< Gen3
MaxPcieGen ///< Max Gen for boundary check
} PCIE_LINK_SPEED_CAP;
/// PCIe PSPP Power policy
typedef enum {
PsppDisabled, ///< PSPP disabled
PsppPerformance = 1, ///< Performance
PsppBalanceHigh, ///< Balance-High
PsppBalanceLow, ///< Balance-Low
PsppPowerSaving, ///< Power Saving
MaxPspp ///< Max Pspp for boundary check
} PCIE_PSPP_POLICY;
/// DDI display connector type
typedef enum {
ConnectorTypeDP, ///< DP
ConnectorTypeEDP, ///< eDP
ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
ConnectorTypeHDMI, ///< HDMI
ConnectorTypeDpToVga, ///< DP-to-VGA
ConnectorTypeDpToLvds, ///< DP-to-LVDS
ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
ConnectorTypeCrt, ///< CRT (VGA)
ConnectorTypeLvds, ///< LVDS
ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init
ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init
ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS)
MaxConnectorType ///< Not valid value, used to verify input
} PCIE_CONNECTOR_TYPE;
/// PCIe link channel type
typedef enum {
ChannelTypeLowLoss, ///< Low Loss
ChannelTypeHighLoss, ///< High Loss
ChannelTypeMob0db, ///< Mobile 0dB
ChannelTypeMob3db, ///< Mobile 3dB
ChannelTypeExt6db, ///< Extended 6dB
ChannelTypeExt8db, ///< Extended 8dB
MaxChannelType ///< Not valid value, used to verify input
} PCIE_CHANNEL_TYPE;
/// PCIe link ASPM
typedef enum {
AspmDisabled, ///< Disabled
AspmL0s, ///< PCIe L0s link state
AspmL1, ///< PCIe L1 link state
AspmL0sL1, ///< PCIe L0s & L1 link state
MaxAspm ///< Not valid value, used to verify input
} PCIE_ASPM_TYPE;
/// PCIe link hotplug support
typedef enum {
HotplugDisabled, ///< Hotplug disable
HotplugBasic, ///< Basic Hotplug
HotplugServer, ///< Server Hotplug
HotplugEnhanced, ///< Enhanced
HotplugInboard, ///< Inboard
MaxHotplug ///< Not valid value, used to verify input
} PCIE_HOTPLUG_TYPE;
/// PCIe link initialization
typedef enum {
PortDisabled, ///< Disable
PortEnabled ///< Enable
} PCIE_PORT_ENABLE;
/// PCIe ACS capability - Access Control Services
typedef enum {
PcieAcsDisabled, ///< Disabled
PcieAcsEnabled, ///< Enabled
} PCIE_ACS_CAP;
/// PCIe ClkPmSupport initialization
typedef enum {
ClkPmSupportDisabled, ///< Disable
ClkPmSupportEnabled ///< Enable
} CLKPM_SUPPORT_ENABLE;
/// DDI Aux channel
typedef enum {
Aux1, ///< Aux1
Aux2, ///< Aux2
Aux3, ///< Aux3
Aux4, ///< Aux4
Aux5, ///< Aux5
Aux6, ///< Aux6
MaxAux ///< Not valid value, used to verify input
} PCIE_AUX_TYPE;
/// DDI Hdp Index
typedef enum {
Hdp1, ///< Hdp1
Hdp2, ///< Hdp2
Hdp3, ///< Hdp3
Hdp4, ///< Hdp4
Hdp5, ///< Hdp5
Hdp6, ///< Hdp6
MaxHdp ///< Not valid value, used to verify input
} PCIE_HDP_TYPE;
/// PCIe_DDI_DATA.Flags definitions
#define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1
#define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training
#define EXT_DISPLAY_PATH_CAPS_HDMI20_PI3EQX1204 0x04 ///< BIT[2] HDMI 2.0 connector
#define EXT_DISPLAY_PATH_CAPS_HDMI20_TISN65DP159RSBT 0x08 ///< BIT[3] HDMI 2.0 connector
/// DP receiver definitions with fixed voltage swing
typedef enum {
DP_VS_0_4V_0DB, ///< 0x00
DP_VS_0_6V_0DB, ///< 0x01
DP_VS_0_8V_0DB, ///< 0x02
DP_VS_1_2V_0DB, ///< 0x03
DP_VS_0_4V_3_5DB = 0x8, ///< 0x08
DP_VS_0_6V_3_5DB, ///< 0x09
DP_VS_0_8V_3_5DB, ///< 0x0a
DP_VS_0_4V_6DB = 0x10, ///< 0x10
DP_VS_0_6V_6DB, ///< 0x11
DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
} DP_FIXED_VOLT_SWING_TYPE;
// definition for eDP 1.4 VSMode
#define EDP_VS_LEGACY_MODE 0 ///< Legacy Mode
#define EDP_VS_LOW_VDIFF_MODE 1 ///< Low Vdiff Training Mode
#define EDP_VS_HIGH_VDIFF_MODE 2 ///< High Vdiff Training Mode
#define EDP_VS_STRETCH_MODE 3 ///< Stretched DP training mode
#define EDP_VS_SINGLE_VDIFF_MODE 4 ///< Single Vdiff Training Mode
#define EDP_VS_VARIABLE_PREM_MODE 5 ///< Single Vdiff Training with Variable Transition Vdiff
/// HDMI re-driver register/value
typedef struct _HDMI_RE_DRIVER_I2C_REG_INFO {
IN UINT8 RegIndex; ///< HDMI re-driver Register Index
IN UINT8 RegVal; ///< HDMI re-driver Register Value
} HDMI_RE_DRIVER_I2C_REG_INFO;
/// AZ I2SBUS select
typedef enum {
GnbAcpI2sBus, ///< I2sBus
GnbAcpAzalia, ///< Azalia
MaxAcp ///< Not valid value, used to verify input
} GNB_ACP_TYPE;
/// AZ I2SBUS pin configuration
typedef enum {
GnbAcp4Tx4RxBluetooth, ///< 4Tx4Rx and Bluetooth
GnbAcp2Tx4RxBluetooth, ///< 2Tx4Rx and Bluetooth
GnbAcp6Tx4RxBluetooth, ///< 6Tx4Rx and Bluetooth
GnbAcpPinNotConfigured ///< Not valid value, used to verify input
} GNB_ACP_AZ_I2SBUS_PIN;
/// Alternative DRAM MAC
typedef enum {
MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC
MAC_700k, ///< Assign 1 to 700k
MAC_600k, ///< Assign 2 to 600k
MAC_500k, ///< Assign 3 to 500k
MAC_400k, ///< Assign 4 to 400k
MAC_300k, ///< Assign 5 to 300k
MAC_200k, ///< Assign 6 to 200k
MAC_UNRESTRICTEDMAC = 8, ///< Assign 8 to Unrestricted MAC
} DRAM_MAXIMUM_ACTIVATE_COUNT;
// Macro for statically initializing various structures
#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect, \
{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
#define PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \
{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
#define PCIE_PORT_DATA_INITIALIZER_GEN3(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport, \
mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration) \
{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
{mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}}
#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0}
#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
#define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags}
///IOMMU requestor ID
typedef struct {
IN UINT16 Bus :8; ///< Bus
IN UINT16 Device :5; ///< Device
IN UINT16 Function :3; ///< Function
} IOMMU_REQUESTOR_ID;
/// IVMD exclusion range descriptor
typedef struct {
IN UINT32 Flags; /**< Descriptor flags
* @li @b Flags[31] - Terminate descriptor array.
* @li @b Flags[30] - Ignore descriptor.
*/
IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start
IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID)
IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range
IN UINT64 RangeLength; ///< Length of exclusion range in bytes
} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
/*----------------------------------------------------------------------------
* GNB configuration info
*----------------------------------------------------------------------------
*/
/// LVDS Misc Control Field
typedef struct {
IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
///< @li FALSE = LVDS 888 panel in LDI mode
///< @li TRUE = LVDS 888 panel in FPDI mode
///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
///< @li FALSE = Lower link and upper link not swap
///< @li TRUE = Lower link and upper link are swapped
///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
IN UINT8 BitDepth:1; ///< Customer may use 888 bit LVDS panel, but the LVDS panel EDID does not support v1.4 so that VBIOS can not decide the panel bit per color
///< @li FALSE = LCD 666 18bit panel
///< @li TRUE = LCD 888 24bit panel
///< @BldCfgItem{BLDCFG_LVDS_BIT_DEPTH}
IN UINT8 ParamOverwriteEn:1; ///< LVDS parameter overwrite enable
///< @li FALSE = LVDS parameter overwrite disable
///< @li TRUE = LVDS parameter overwrite enable
///< @BldCfgItem{BLDCFG_LVDS_PARAM_OVERWRITE_EN}
IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
///< @li FALSE = Not inverted(active high)
///< @li TRUE = Inverted (active low)
///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
IN UINT8 LvdsVoltOverwriteEn:1; ///< This item configures polarity of DP-to-LVDS output voltage overwrite
///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting.
///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4
///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE}
IN UINT8 Reserved:2; ///< Reserved
} LVDS_MISC_CONTROL_FIELD;
/// LVDS Misc Control
typedef union _LVDS_MISC_CONTROL {
IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
IN UINT8 Value; ///< LVDS Misc Control Value
} LVDS_MISC_CONTROL;
/// Display Misc Control Field
typedef struct {
IN UINT8 Reserved1:3; ///< Reserved
IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open.
///< @li FALSE = VBIOS fast boot is disable.
///< @li TRUE = VBIOS fast boot is enable.
///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE}
IN UINT8 Reserved2:4; ///< Reserved
} DISPLAY_MISC_CONTROL_FIELD;
/// LVDS Misc Control
typedef union _DISPLAY_MISC_CONTROL {
IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD
IN UINT8 Value; ///< Display Misc Control Value
} DISPLAY_MISC_CONTROL;
/// HD Audio Codec table list
typedef struct _CODEC_VERB_TABLE_LIST {
IN UINT32 CodecId; ///< CodecID - Codec ID
IN UINT32 CodecTablePtr; ///< CodecTablePtr - Codec table pointer
} CODEC_VERB_TABLE_LIST;
/// POST Configuration settings for GNB.
typedef struct {
IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
///< @li 0 = Auto - use existing default -
///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present
///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
} GNB_POST_CONFIGURATION;
/// iGPU Enable/Disable Policy values
#define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
#define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present
/// ENV Configuration settings for GNB.
typedef struct {
IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
///< @li 0 = Stereo 3D is disabled (default).
///< @li 1 = Use processor pin HPD1.
///< @li 2 = Use processor pin HPD2
///< @li 3 = Use processor pin HPD3
///< @li 4 = Use processor pin HPD4
///< @li 5 = Use processor pin HPD5
///< @li 6 = Use processor pin HPD6
///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
IN BOOLEAN IommuSupport; ///< IOMMU support.
///< @li FALSE = Disabled. Disable and hide IOMMU device.
///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported.
///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings.
///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode.
///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support
///< @li TRUE = Enable Wireless Display Support
///< @li FALSE = Disable Wireless Display Support
///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
IN UINT8 LvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control
IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value
///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
IN UINT32 GpuFrequencyLimit; ///< GNB GPU Max Frequency(NULL if platform configured)
///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
IN UINT8 EDPv1_4VSMode; ///< @BldCfgItem{BLDCFG_EDP_V1_4_VS_MODE}
IN UINT8 ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR}
IN UINT8 ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM}
IN UINT64 ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO}
} GNB_ENV_CONFIGURATION;
/// Configuration settings for GNB.
typedef struct {
IN UINT8 iGpuVgaMode; ///< VGA resources decoding configuration for iGPU
///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter)
///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
IN UINT8 PcieAcsCapability; ///< Pcie ACS Capability support
///< @li 0 = Disabled
///< @li 1 = Enabled
IN UINT64 GnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
IN UINT8 MaxNumAudioEndpoints; ///< Max number of audio endpoints
///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS}
} GNB_MID_CONFIGURATION;
/// GNB configuration info
typedef struct {
IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
* Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
* Example of topology definition for single socket system:
* @code
* PCIe_PORT_DESCRIPTOR PortList [] = {
* // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
* PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
* },
* // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
* PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
* },
* // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
* PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
* }
* };
* PCIe_PORT_DESCRIPTOR DdiList [] = {
* // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
* {
* 0, //Descriptor flags
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
* },
* // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
* {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
* PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
* }
* };
* PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
* DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
* 0, //Socket ID
* &PortList[0],
* &DdiList[0],
* }
* @endcode
*/
IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
* @li @b 0 - Disabled
* @li @b 1 - Performance
* @li @b 2 - Balance-High
* @li @b 3 - Balance-Low
* @li @b 4 - Power Saving
*/
} GNB_CONFIGURATION;
/// Late Configuration settings for GNB.
typedef struct {
IN BOOLEAN Reserved; ///< Reserved -- Docked TDP headroom
IN UINT8 GnbIoapicId; ///< GNB IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
///< If BLDCFG_GNB_IOAPIC_ADDRESS == NULL or BLDCFG_IOMMU_SUPPORT == NULL or GnbIoapicId == default(0xFF), AGESA will skip it anyway.
///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
IN UINT8 FchIoapicId; ///< Fch IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
///< If BLDCFG_IOMMU_SUPPORT == NULL or or FchIoapicId == default(0xFF), AGESA will skip it anyway.
///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
} GNB_LATE_CONFIGURATION;
//
// MEMORY-SPECIFIC DATA STRUCTURES
//
//
//
//
// AGESA MAXIMIUM VALUES
//
// These Max values are used to define array sizes and associated loop
// counts in the code. They reflect the maximum values that AGESA
// currently supports and does not necessarily reflect the hardware
// capabilities of configuration.
//
#define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system
#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
///< Eg: UINT16 *RcvEnDlys;
///< UINT8 *WrDqsDlys;
///< UINT8 *RdDqsDlys;
///< UINT8 *WrDatDlys;
///< UINT8 *RdDqsMinDlys;
///< UINT8 *RdDqsMaxDlys;
///< UINT8 *WrDatMinDlys;
///< UINT8 *WrDatMaxDlys;
#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8]
#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8]
#define DATAEYE_VREF_RANGE 31 ///< Number of VREF steps in Data Eye Bitmap
#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved
#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0
#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1
#define UMA_ATTRIBUTE_ON_DCT2 0x10000000ul ///< UMA resides on memory that belongs to DCT2
#define UMA_ATTRIBUTE_ON_DCT3 0x08000000ul ///< UMA resides on memory that belongs to DCT3
typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
// AGESA DEFINITIONS
//
// Many of these are derived from the platform and hardware specific definitions
/// EccSymbolSize override value
#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
/// CPU Package Type
#define PT_L1 0 ///< L1 Package type
#define PT_M2 1 ///< AM Package type
#define PT_S1 2 ///< S1 Package type
/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
/// Build Configuration limit for BLDCFG_GNB_GPU_MAX_FREQUENCY
#define UNSUPPORTED_GPU_FREQUENCY 901 ///< Highest limit of GPU frequency
/// Structures use to pass system Logical CPU-ID
typedef struct {
IN OUT UINT16 Family; ///< Indicates logical ID Family
IN OUT UINT16 Revision; ///< Indicates logical ID Family
} CPU_LOGICAL_ID;
/// Structures use to report AMP status
typedef struct {
OUT BOOLEAN AmpVoltageValid; ///< Indicates if Amp voltage is valid
OUT BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled
OUT BOOLEAN AmpSelectedButNotEnabled; ///< Indicates if Amp is selected but not enabled
} AMP_STATUS;
/// Normalized Critical Composite Data Eye
/// Bit 15 represents trained eye Center
/// Bit 0 represents eye center -15 delay steps
/// Bit 31 represents eye center +16 delay steps
/// Offset 0 represents +15 Vref Steps
/// Offset 31 represents -15 Vref Steps
typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE];
/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
typedef enum {
AMD_PLATFORM_SERVER = 0x8000, ///< Server
AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
} AMD_PLATFORM_TYPE;
/// Dram technology type
typedef enum {
DDR2_TECHNOLOGY, ///< DDR2 technology
DDR3_TECHNOLOGY, ///< DDR3 technology
GDDR5_TECHNOLOGY, ///< GDDR5 technology
DDR4_TECHNOLOGY, ///< DDR4 technology
UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
} TECHNOLOGY_TYPE;
/// Low voltage support
typedef enum {
VOLT_INITIAL, ///< Initial value for VDDIO
VOLT1_5, ///< 1.5 Volt
VOLT1_35, ///< 1.35 Volt
VOLT1_25, ///< 1.25 Volt
VOLT_DDR4_RANGE_START, ///< Start of DDR4 Voltage Range
VOLT1_2 = VOLT_DDR4_RANGE_START, ///< 1.2 Volt
VOLT_TBD1, ///< TBD1 Voltage
VOLT_TBD2, ///< TBD2 Voltage
VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
} DIMM_VOLTAGE;
/// AMP voltage support
typedef enum {
AMP_VOLT_RSVD, ///< Reserved
AMP_VOLT1_5, ///< 1.5 Volt
AMP_VOLT1_55, ///< 1.55 Volt
AMP_VOLT1_6, ///< 1.6 Volt
AMP_VOLT1_65, ///< 1.65 Volt
AMP_VOLT1_7, ///< 1.7 Volt
AMP_VOLT1_75, ///< 1.75 Volt
AMP_VOLT1_8, ///< 1.8 Volt
AMP_VOLT1_85, ///< 1.85 Volt
AMP_VOLT1_9, ///< 1.9 Volt
AMP_VOLT1_45 = 0x10, ///< 1.45 Volt
AMP_VOLT1_4 = 0x20, ///< 1.4 Volt
AMP_VOLT1_35 = 0x30, ///< 1.35 Volt
AMP_VOLT1_3 = 0x40, ///< 1.3 Volt
AMP_VOLT1_25 = 0x50, ///< 1.25 Volt
AMP_VOLT1_2 = 0x60 ///< 1.2 Volt
} AMP_DIMM_VOLTAGE;
/// Build Configuration values for BLDCFG_RESOLUTION
typedef enum {
DISPLAY_1920x1080_And_Below = 0, ///< 1920x1080 and below
DISPLAY_2560x1600 = 1, ///< 2560x1600
DISPLAY_3840x2160 = 2 ///< 3840x2160
} DISPLAY_RESOLUTION;
/// Build Configuration values for BLDCFG_ACP_SIZE
typedef enum {
NO_ACP_SIZE = 0x00, ///< NO ACP
ACP_SIZE_2MB = 0x20, ///< UMA 4MB aligned
ACP_SIZE_4MB = 0x40, ///< UMA 128MB aligned
} ACP_SIZE;
/// UMA Version
typedef enum {
UMA_LEGACY = 0, ///< UMA Legacy Version
UMA_NON_LEGACY = 1 ///< UMA Non Legacy Version
} UMA_VERSION;
/// UMA Mode
typedef enum {
UMA_NONE = 0, ///< UMA None
UMA_SPECIFIED = 1, ///< UMA Specified
UMA_AUTO = 2 ///< UMA Auto
} UMA_MODE;
/// Force Training Mode
typedef enum {
FORCE_TRAIN_1D = 0, ///< 1D Training only
FORCE_TRAIN_2D = 1, ///< 2D Training only
FORCE_TRAIN_AUTO = 2 ///< Auto - 1D or 2D depending on configuration
} FORCE_TRAIN_MODE;
/// PMU Training Mode
typedef enum {
PMU_TRAIN_1D = 0, ///< PMU 1D Training only
PMU_TRAIN_1D_2D_READ = 1, ///< PMU 1D and 2D Training read only
PMU_TRAIN_1D_2D = 2, ///< PMU 1D and 2D Training
PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration
} PMU_TRAIN_MODE;
/// The possible DRAM prefetch mode settings.
typedef enum {
DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only.
DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only.
DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching.
MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking.
} DRAM_PREFETCH_MODE;
/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
typedef enum {
NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned
UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
} UMA_ALIGNMENT;
///
/// Global MCT Configuration Status Word (GStatus)
///
typedef enum {
GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
GsbDramECCDis, ///< Dram ECC requested but not enabled.
GsbSoftHole, ///< A Node Base gap was created
GsbHWHole, ///< A HW dram remap was created
GsbNodeIntlv, ///< Node Memory interleaving was enabled
GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
GsbEOL ///< End of list
} GLOBAL_STATUS_FIELD;
///
/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
///
typedef enum {
EsbNoDimms, ///< No DIMMs
EsbSpdChkSum, ///< SPD Checksum fail
EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
EsbDimmMismatchT, ///< dimm CL/T mismatch
EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
EsbNoCycTime, ///< SPD missing byte 23 or 25
EsbBkIntDis, ///< Bank interleave requested but not enabled
EsbDramECCDis, ///< Dram ECC requested but not enabled
EsbSpareDis, ///< Online spare requested but not enabled
EsbMinimumMode, ///< Running in Minimum Mode
EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
EsbNoDqsPos, ///< No DQS-DQ passing positions
EsbSmallDqs, ///< DQS-DQ passing window too small
EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
EsbEMPNotSupported, ///< Processor is not capable for EMP.
EsbEMPConflict, ///< EMP requested but cannot be enabled since
///< channel interleaving, bank interleaving, or bank swizzle is enabled.
EsbEMPDis, ///< EMP requested but cannot be enabled since
///< memory size of each DCT is not a power of two.
EsbEOL ///< End of list
} ERROR_STATUS_FIELD;
///
/// Local Configuration Status (DIE_STRUCT.Status[31:0])
///
typedef enum {
SbRegistered, ///< All DIMMs are Registered
SbEccDimms, ///< All banks ECC capable
SbParDimms, ///< All banks Addr/CMD Parity capable
SbDiagClks, ///< Jedec ALL slots clock enable diag mode
Sb128bitmode, ///< DCT in 128-bit mode operation
Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
Sb2TMode, ///< 2T CMD timing mode is enabled.
SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
SbHWHole, ///< Memory Hole created on this Node using HW remapping.
SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
SbLrdimms, ///< All DIMMs are LRDIMMs
SbEOL ///< End of list
} LOCAL_STATUS_FIELD;
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010ul
#define TOP_MEM 0xC001001Aul
#define TOP_MEM2 0xC001001Dul
#define HWCR 0xC0010015ul
#define NB_CFG 0xC001001Ful
#define FS_BASE 0xC0000100ul
#define IORR0_BASE 0xC0010016ul
#define IORR0_MASK 0xC0010017ul
#define BU_CFG 0xC0011023ul
#define BU_CFG2 0xC001102Aul
#define COFVID_STAT 0xC0010071ul
#define TSC 0x10
//-----------------------------------------------------------------------------
///
/// SPD Data for each DIMM.
///
typedef struct _SPD_DEF_STRUCT {
IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to
///< 0 = Lower Page
///< 1 = Upper Page (DDR4 Only)
IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
} SPD_DEF_STRUCT;
//-----------------------------------------------------------------------------
///
/// VDDP_VDDR Voltage Info for Low Power DIMM
///
typedef struct _VDDP_VDDR_VOLTAGE {
IN BOOLEAN IsValid; ///< Indicates if daata is valid
IN UINT8 Voltage; ///< VDDP VDDR Voltage Value
} VDDP_VDDR_VOLTAGE;
///
/// Channel Definition Structure.
/// This data structure defines entries that are specific to the channel initialization
///
typedef struct _CH_DEF_STRUCT {
OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
///< DIMM# Select Signal
///< 0 MA0_CS_L[0, 1]
///< 1 MB0_CS_L[0, 1]
///< 2 MA1_CS_L[0, 1]
///< 3 MB1_CS_L[0, 1]
///< 4 MA2_CS_L[0, 1]
///< 5 MB2_CS_L[0, 1]
///< 6 MA3_CS_L[0, 1]
///< 7 MB3_CS_L[0, 1]
OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
///<
OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
OUT UINT8 Loads; ///< Number of devices loading bus
OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
OUT BOOLEAN SlowModePs1; ///< 1T or 2T CMD mode (slow access mode) for Mem Pstate 1
///< FALSE = 1T
///< TRUE = 2T
///< The following pointers will be pointed to dynamically allocated buffers.
///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
///< Example: If DIMM and Byte based training, then
///< XX is a value in Hex
///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
OUT UINT8 *WrDatDlys; ///< Write Data delays
OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data
OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1
OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1
OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1
OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1
OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1
OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1
OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1
OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1
OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1
OUT VOID *RdDataEyes; ///< Pointer to Read Data Eye Bitmaps
OUT VOID *WrDataEyes; ///< Pointer to Write Data Eye Bitmaps
OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
OUT UINT32 DctAddrTmgPs1; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) for Mem Pstate 1
OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
OUT UINT8 Pattern; ///< Current pattern
OUT UINT8 DqsDelay; ///< Current DQS delay value
OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT
///< DctMaxRdLat [i] is for NBPstate i
OUT UINT8 DIMMValidCh; ///< DIMM# in CH
OUT UINT8 MaxCh; ///< Max number of CH in system
OUT UINT8 Dct; ///< Dct pointer
OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
OUT UINT32 NodeSysBase; ///< for channel interleave usage
OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
///< base on this array to disable unused MemClk to save power.
///<
///< The array must have 8 entries. Each entry, which associates with
///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
///< Example:
///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
///< is like below:
///< Bit AM3/S1g3 pin name
///< 0 M[B,A]_CLK_H/L[0]
///< 1 M[B,A]_CLK_H/L[1]
///< 2 M[B,A]_CLK_H/L[2]
///< 3 M[B,A]_CLK_H/L[3]
///< 4 M[B,A]_CLK_H/L[4]
///< 5 M[B,A]_CLK_H/L[5]
///< 6 M[B,A]_CLK_H/L[6]
///< 7 M[B,A]_CLK_H/L[7]
///< And platform has the following routing:
///< CS0 M[B,A]_CLK_H/L[4]
///< CS1 M[B,A]_CLK_H/L[2]
///< CS2 M[B,A]_CLK_H/L[3]
///< CS3 M[B,A]_CLK_H/L[5]
///< Then MemClkDisMap should be pointed to the following array:
///< CLK_2 CLK_3 CLK_4 CLK_5
///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
///< Each entry of the array is the bitmask of 8 chip selects.
OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
///< the routing of CKE pins to the DIMMs' ranks.
///< The array must have 2 entries. Each entry, which associates with
///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
///< AGESA will base on this array to disable unused CKE pins to save power.
OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
///< the routing of ODT pins to the DIMMs' ranks.
///< The array must have 4 entries. Each entry, which associates with
///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
///< AGESA will base on this array to disable unused ODT pins to save power.
OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
///< the routing of chip select pins to the DIMMs' ranks.
///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
///< AGESA will base on this array to disable unused Chip select pins to save power.
OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved
OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved
OUT UINT8 DimmThermSensorPresent; ///< For each bit n 0..3, 1 = DIMM n has an On Dimm Thermal Sensor where 4..7 are reserved
OUT UINT8 MaxVref; ///< Maximum Vref Value for channel
OUT UINT8 Reserved[100]; ///< Reserved
} CH_DEF_STRUCT;
///
/// DCT Channel Timing Parameters.
/// This data structure sets timings that are specific to the channel.
///
typedef struct _CH_TIMING_STRUCT {
OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
OUT UINT16 DIMMTrrdL; ///< Minimax TrrdL*40 (ns) of DIMMs
OUT UINT16 DIMMTwtrL; ///< Minimax TtwrL*40 (ns) of DIMMs
OUT UINT16 DIMMTccdL; ///< Minimax TccdL*40 (ns) of DIMMs
OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
OUT UINT16 Speed; ///< DRAM bus speed in MHz
///< 400 (MHz)
///< 533 (MHz)
///< 667 (MHz)
///< 800 (MHz)
///< and so on...
OUT UINT8 Trcpage; ///< DCT Trcpage (10 ns)
OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
OUT UINT8 Trp; ///< DCT Trp (busclocks)
OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
OUT UINT8 Tras; ///< DCT Tras (busclocks)
OUT UINT8 Trc; ///< DCT Trc (busclocks)
OUT UINT8 Twr; ///< DCT Twr (busclocks)
OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
OUT UINT8 TrrdL; ///< DCT TrrdL (busclocks)
OUT UINT8 TwtrL; ///< DCT TwtrL (busclocks)
OUT UINT8 TccdL; ///< DCT TccdL (busclocks)
OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns)
OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns)
OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns)
OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns)
OUT UINT16 Trfc4; ///< DCT Trfc4min All DIMMS (in ns) - DDR4 Only
OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
///<
OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
///< FALSE = 1T
///< TRUE = 2T
OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
OUT UINT16 MaxRdLat0; ///< Max Read Latency 0
OUT UINT16 MaxRdLat1; ///< Max Read Latency 1
OUT UINT16 MaxRdLat2; ///< Max Read Latency 2
OUT UINT16 MaxRdLat3; ///< Max Read Latency 3
OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
} CH_TIMING_STRUCT;
///
/// Data for each DCT.
/// This data structure defines data used to configure each DRAM controller.
///
typedef struct _DCT_STRUCT {
OUT UINT8 Dct; ///< Current Dct
OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1
OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
OUT UINT8 ChannelCount; ///< Number of channel per this DCT
OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT
OUT UINT8 BankAddrMap; ///< Bank Address Mapping
OUT UINT8 EnabledChipSels; ///< Number of enabled chip selects on current DCT
} DCT_STRUCT;
///
/// Data Structure defining each Die.
/// This data structure contains information that is used to configure each Die.
///
typedef struct _DIE_STRUCT {
/// Advanced:
OUT UINT8 NodeId; ///< Node ID of current controller
OUT UINT8 SocketId; ///< Socket ID of this Die
OUT UINT8 DieId; ///< ID of this die relative to the socket
OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
///< 0x0 = AGESA_SUCCESS
///< 0x1 = AGESA_UNSUPPORTED
///< 0x2 = AGESA_BOUNDS_CHK
///< 0x3 = AGESA_ALERT
///< 0x4 = AGESA_WARNING
///< 0x5 = AGESA_ERROR
///< 0x6 = AGESA_CRITICAL
///< 0x7 = AGESA_FATAL
///<
OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
///<
OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
///<
OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
///<
OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
///<
OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
///<
OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
///<
OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
///< DIMM# Select Signal
///< 0 MA0_CS_L[0, 1]
///< 1 MB0_CS_L[0, 1]
///< 2 MA1_CS_L[0, 1]
///< 3 MB1_CS_L[0, 1]
///< 4 MA2_CS_L[0, 1]
///< 5 MB2_CS_L[0, 1]
///< 6 MA3_CS_L[0, 1]
///< 7 MB3_CS_L[0, 1]
///<
OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
///<
OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
///< 0 in any bit field indicates Channel 0
///< 1 in any bit field indicates Channel 1
OUT UINT8 Dct; ///< Need to be removed
///< DCT pointer
OUT BOOLEAN GangedMode; ///< Ganged mode
///< 0 = disabled
///< 1 = enabled
OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
///<
OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
///<
OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
///<
OUT UINT8 MLoad; ///< Need to be removed
///< Number of devices loading MAA bus
///<
OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
///<
OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
///<
OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
///<
OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
OUT UINT8 DctCount; ///< Number of DCTs per this Die
OUT UINT8 Reserved[16]; ///< Reserved
} DIE_STRUCT;
/**********************************************************************
* S3 data block structure
**********************************************************************/
/// AmdInitResume, AmdS3LateRestore, and AmdInitRtb param structure
typedef struct {
OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
OUT UINT16 Version; ///< S3 Params version number
IN OUT UINT32 Flags; ///< Indicates operation
IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
} S3_DATA_BLOCK;
/// Header at the beginning of a context save buffer.
typedef struct {
_2BYTE_ALIGN UINT16 Version; ///< Version of header
_4BYTE_ALIGN UINT32 Revision; ///< Revision of the S3 data blob
_2BYTE_ALIGN UINT16 NumDevices; ///< Number of devices in the list
_2BYTE_ALIGN UINT16 RelativeOrMaskOffset; ///< Size of device list + header
_4BYTE_ALIGN UINT32 BlobSize; ///