/* $NoKeywords:$ */ /** * @file * * mpmr0.c * * A sub-engine which extracts MR0[WR] and MR0[CL] value. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: (Mem/Ps) * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * **/ /***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. If you do not agree to the terms and conditions of the Software * License Agreement, please do not use any portion of these Materials. * * CONFIDENTIALITY: The Materials and all other information, identified as * confidential and provided to you by AMD shall be kept confidential in * accordance with the terms and conditions of the Software License Agreement. * * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. * * AMD does not assume any responsibility for any errors which may appear in * the Materials or any other related information provided to you by AMD, or * result from use of the Materials or any related information. * * You agree that you will not reverse engineer or decompile the Materials. * * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any * further information, software, technical information, know-how, or show-how * available to you. Additionally, AMD retains the right to modify the * Materials at any time, without notice, and is not obligated to provide such * modified Materials to you. * * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is * subject to the restrictions as set forth in FAR 52.227-14 and * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. * *************************************************************************** * */ /* *---------------------------------------------------------------------------- * MODULES USED * *---------------------------------------------------------------------------- */ #include "AGESA.h" #include "AdvancedApi.h" #include "amdlib.h" #include "Ids.h" #include "OptionMemory.h" #include "PlatformMemoryConfiguration.h" #include "ma.h" #include "mp.h" #include "merrhdl.h" #include "GeneralServices.h" #include "Filecode.h" CODE_GROUP (G2_PEI) RDATA_GROUP (G2_PEI) #define FILECODE PROC_MEM_PS_MPMR0_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * PROTOTYPES OF LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */ BOOLEAN MemPGetMR0WrCL ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ); /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * *---------------------------------------------------------------------------- */ /* -----------------------------------------------------------------------------*/ /** * * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the * value to a specific address. * * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK * * @return TRUE - Succeed in extracting the table value * @return FALSE - Fail to extract the table value * */ BOOLEAN MemPGetMR0WrCL ( IN OUT MEM_NB_BLOCK *NBPtr, IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; UINT8 j; UINT8 p; UINT32 Value32; UINT8 TableSize; PSCFG_TYPE Type; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; UINT8 PsoMaskMR0; PSCFG_MR0CL_ENTRY *TblPtr; PSC_TBL_ENTRY **ptr; CH_DEF_STRUCT *CurrentChannel; CurrentChannel = NBPtr->ChannelPtr; TblPtr = NULL; TableSize = 0; PsoMaskMR0 = 0; // Extract MR0[WR] value, then MR0[CL] value for (i = 0; i < 2; i++) { if (i == 0) { ptr = EntryOfTables->TblEntryOfMR0WR; Type = PSCFG_MR0WR; } else { ptr = EntryOfTables->TblEntryOfMR0CL; Type = PSCFG_MR0CL; } p = 0; // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type. while (ptr[p] != NULL) { // // Determine if this is the expected NB Type // LogicalCpuid = (ptr[p])->Header.LogicalCpuid; PackageType = (ptr[p])->Header.PackageType; if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) { TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr); TableSize = (ptr[p])->TableSize; break; } p++; } // Check whether no table entry is found. if (ptr[p] == NULL) { IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n"); return FALSE; } Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl); for (j = 0; j < TableSize; j++, TblPtr++) { if (Value32 == (UINT32) TblPtr->Timing) { if (Type == PSCFG_MR0WR) { NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value; break; } else { NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value; NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1; break; } } } // // If there is no entry, check if overriding value existed. If not, return FALSE. // PsoMaskMR0 = (UINT8) MemPProceedTblDrvOverride (NBPtr, NBPtr->RefPtr->PlatformMemoryConfiguration, ((i == 0) ? PSO_TBLDRV_MR0_WR : PSO_TBLDRV_MR0_CL)); if ((PsoMaskMR0 == 0) && (j == TableSize)) { IDS_HDT_CONSOLE (MEM_FLOW, (i == 0) ? "\nNo MR0[WR] entries\n" : "\nNo MR0[CL] entries\n"); PutEventLog (AGESA_ERROR, MEM_ERROR_MR0_NOT_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); SetMemError (AGESA_ERROR, NBPtr->MCTPtr); if (!NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) { ASSERT (FALSE); } return FALSE; } } return TRUE; }