/** * @file * * ALIB PSPP Pcie Smu Lib V1 * * * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. If you do not agree to the terms and conditions of the Software * License Agreement, please do not use any portion of these Materials. * * CONFIDENTIALITY: The Materials and all other information, identified as * confidential and provided to you by AMD shall be kept confidential in * accordance with the terms and conditions of the Software License Agreement. * * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. * * AMD does not assume any responsibility for any errors which may appear in * the Materials or any other related information provided to you by AMD, or * result from use of the Materials or any related information. * * You agree that you will not reverse engineer or decompile the Materials. * * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any * further information, software, technical information, know-how, or show-how * available to you. Additionally, AMD retains the right to modify the * Materials at any time, without notice, and is not obligated to provide such * modified Materials to you. * * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is * subject to the restrictions as set forth in FAR 52.227-14 and * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. * *************************************************************************** * */ /*----------------------------------------------------------------------------------------*/ /** * SMU indirect register read * * Arg0 - Smu register offset * */ Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) // Access 32 bit width Increment (Arg0) // Reverse ReqToggle Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) // Assign Address and ReqType = 0 Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) return (Local0) } /*----------------------------------------------------------------------------------------*/ /** * SMU indirect register Write * * Arg0 - Smu register offset * Arg1 - Value * Arg2 - Width, 0 = 16, 1 = 32 * */ Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) // Get low 16 bit value Store (And (Arg1, 0xFFFF), Local1) // Reverse ReqToggle Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) // Assign Address Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) // ReqType = 1 Or (Local0, 0x02000000, Local0) // Assign Low 16 bit value Or (Local0, Local1, Local0) procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) if (LEqual (Arg2, 1)) { // Get high 16 bit value Store (ShiftRight (Arg1, 16), Local1) // Reverse ReqToggle Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) // Assign Address Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) // Assign High 16 bit value Or (Local0, Local1, Local0) procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) } } /*----------------------------------------------------------------------------------------*/ /** * SMU Service request * * Arg0 - Smu service id * Arg1 - Flags - Poll Ack = 1, Poll down = 2 * */ Method (procNbSmuServiceRequest, 2, NotSerialized) { Store ("NbSmuServiceRequest Enter", Debug) Store ("Request id =", Debug) Store (Arg0, Debug) Or (ShiftLeft (Arg0, 3), 0x1, Local0) procNbSmuIndirectRegisterWrite (0x3, Local0, 1) if (LAnd (Arg1, 1)) { while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { Store ("--Wait Ack--", Debug) } } if (LAnd (Arg1, 2)) { while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { Store ("--Wait Done--", Debug) } } // Clear IRQ register procNbSmuIndirectRegisterWrite (0x3, 0, 1) Store ("NbSmuServiceRequest Exit", Debug) } /*----------------------------------------------------------------------------------------*/ /** * Write RCU register * * Arg0 - Register Address * Arg1 - Register Data * */ Method (procSmuRcuWrite, 2, NotSerialized) { procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) } /*----------------------------------------------------------------------------------------*/ /** * Read RCU register * * Arg0 - Register Address * Retval - RCU register value */ Method (procSmuRcuRead, 1, NotSerialized) { procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) Store (procNbSmuIndirectRegisterRead (0x5), Local0) return (Local0) } /*----------------------------------------------------------------------------------------*/ /** * SMU SRBM Register Read * * Arg0 - FCR register address * */ Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { //SMUx0B_x8600 Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) //SMUx0B_x8604 Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) //SMUx0B_x8608 Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) //Write SMU RCU procSmuRcuWrite (0x8600, Local0) procSmuRcuWrite (0x8604, Local1) procSmuRcuWrite (0x8608, Local2) // ServiceId if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { procNbSmuServiceRequest (0xD, 0x3) } if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { procNbSmuServiceRequest (0xB, 0x3) } return (procSmuRcuRead(0x8650)) } /*----------------------------------------------------------------------------------------*/ /** * SMU SRBM Register Write * * Arg0 - FCR register address * Arg1 - Value * */ Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { //SMUx0B_x8600 Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) //SMUx0B_x8604 Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) //SMUx0B_x8608 Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) Or (Local2, ShiftLeft (1, 16), Local2) //Write SMU RCU procSmuRcuWrite (0x8600, Local0) procSmuRcuWrite (0x8604, Local1) procSmuRcuWrite (0x8608, Local2) //Write Data procSmuRcuWrite (0x8650, Arg1) // ServiceId procNbSmuServiceRequest (0xB, 0x3) }