/* $NoKeywords:$ */ /** * @file * * Config Hudson2 Pcie controller * * Init GPP (pcie Controller) features. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. **************************************************************************** */ #include "FchPlatform.h" #include "Filecode.h" #define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE /** * ProgramFchGppInitReset - Config Gpp at PowerOnReset * * * @param[in] FchGpp Pointer to Fch GPP configuration structure * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS * */ VOID ProgramFchGppInitReset ( IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader ) { // // Toggle GEVENT4 to reset all GPP devices // ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); if (FchGpp->SerialDebugBusEnable) { RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), (UINT32)~BIT12, 0x00); } } /** * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device * reset * * * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE * @param[in] ResetOp - Assert or deassert PCIE reset * @param[in] StdHeader * */ VOID FchResetPcie ( IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 Or8; UINT8 Mask8; if (ResetBlock == NbBlock) { if (ResetOp == AssertReset) { Or8 = BIT4; Mask8 = 0; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); } else if (ResetOp == DeassertReset) { Or8 = 0; Mask8 = BIT4; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); } } else if (ResetBlock == FchBlock) { Or8 = BIT1; Mask8 = BIT1 + BIT0; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); if (ResetOp == AssertReset) { Or8 = 0; Mask8 = BIT5; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); Or8 = BIT4; Mask8 = 0; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); } else if (ResetOp == DeassertReset) { Or8 = 0; Mask8 = BIT4; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); Or8 = BIT5; Mask8 = 0; LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); } } }