/* $NoKeywords:$ */ /** * @file * * Config Fch Pcib controller * * Init Pcib Controller features (PEI phase). * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: FCH * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. **************************************************************************** */ #include "FchPlatform.h" #define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE /** * FchInitResetPcibPciTable - Pcib device registers initial * during the power on stage. * * * * */ REG8_MASK FchInitResetPcibPciTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) // {0x00, PCIB_BUS_DEV_FUN, 0}, {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, {FCH_PCIB_REG40, 0xDF, 0x20}, {0x50 , 0x02, 0x01}, {0xFF, 0xFF, 0xFF}, }; /** * FchInitResetPcib - Config Pcib controller during Power-On * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetPcib ( IN VOID *FchDataPtr ) { AMD_CONFIG_PARAMS *StdHeader; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetPcibPciTable[0]), sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK), StdHeader ); if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) { FchInitResetPcibPort80Enable (FchDataPtr); } } /** * FchInitResetPcibPort80Enable - Pcib device registers initial * during the power on stage. * * * * */ REG8_MASK FchInitResetPcibPort80EnableTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) // {0x00, PCIB_BUS_DEV_FUN, 0}, {0x1C , 0x00, 0xF0}, {0x1D , 0x00, 0x00}, {0x04 , 0x00, 0x21}, {0xFF, 0xFF, 0xFF}, }; /** * FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetPcibPort80Enable ( IN VOID *FchDataPtr ) { AMD_CONFIG_PARAMS *StdHeader; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]), sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK), StdHeader ); }