/* $NoKeywords:$ */
/**
 * @file
 *
 * Config Fch Pcib controller
 *
 * Init Pcib Controller features.
 *
 * @xrefitem bom "File Content Label" "Release Content"
 * @e project:     AGESA
 * @e sub-project: FCH
 * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
 *
 */
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*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBLATE_FILECODE

/**
 * FchInitLatePcib - Prepare Pcib controller to boot to OS.
 *
 * @param[in] FchDataPtr Fch configuration structure pointer.
 *
 */
VOID
FchInitLatePcib (
  IN  VOID     *FchDataPtr
  )
{
  UINT8        Value;
  UINT8        NStBit;
  UINT8        NSBit;
  UINT32       VarDd;
  FCH_DATA_BLOCK         *LocalCfgPtr;
  AMD_CONFIG_PARAMS      *StdHeader;

  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
  StdHeader = LocalCfgPtr->StdHeader;

  //
  // We need to do the following setting in late post also because some bios core pci enumeration changes these values
  // programmed during early post.
  //  Master Latency Timer
  //
  Value = 0x40;
  WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader);
  WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader);

  //
  // CLKRUN#
  // FCH P2P AutoClock control settings.
  // VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow);
  //
  if ( LocalCfgPtr->Pcib.PcibClockRun ) {
    ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value);
    NStBit = Value & 0x03;
    NSBit = (Value & 0x3F ) >> 2;
    VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;

    VarDd = 9; // for A12
    WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader);
  }

  VarDd = (LocalCfgPtr->Pcib.PcibClkStopOverride);
  RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x50 , AccessWidth16, 0x3F, (UINT16) (VarDd << 6), StdHeader);
}