/* $NoKeywords:$ */
/**
* @file
*
* FCH IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*;********************************************************************************
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#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
/*----------------------------------------------------------------------------------------*/
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
* @param[in] StdHeader
*
*/
VOID
ProgramPciByteTable (
IN REG8_MASK *pPciByteTable,
IN UINT16 dwTableSize,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 dbBusNo;
UINT8 dbDevFnNo;
UINT8 Or8;
UINT8 Mask8;
PCI_ADDR PciAddress;
dbBusNo = pPciByteTable->RegIndex;
dbDevFnNo = pPciByteTable->AndMask;
pPciByteTable++;
for ( i = 1; i < dwTableSize; i++ ) {
if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
pPciByteTable++;
dbBusNo = pPciByteTable->RegIndex;
dbDevFnNo = pPciByteTable->AndMask;
pPciByteTable++;
i++;
} else {
PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
Or8 = pPciByteTable->OrMask;
Mask8 = ~pPciByteTable->AndMask;
LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
pPciByteTable++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
* @param[in] StdHeader
*
*/
VOID
ProgramFchAcpiMmioTbl (
IN ACPI_REG_WRITE *pAcpiTbl,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 Or8;
UINT8 Mask8;
UINT32 ddtempVar;
if (pAcpiTbl != NULL) {
if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
// Signature Checking
pAcpiTbl++;
for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
Or8 = pAcpiTbl->DataOrMask;
Mask8 = ~pAcpiTbl->DataAndMask;
LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
pAcpiTbl++;
}
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
*
*
*
* @param[in] pSciMapTbl - Table data pointer
* @param[in] FchResetDataBlock
*
*/
VOID
ProgramFchSciMapTbl (
IN SCI_MAP_CONTROL *pSciMapTbl,
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
)
{
AMD_CONFIG_PARAMS *StdHeader;
UINT32 ddtempVar;
StdHeader = FchResetDataBlock->StdHeader;
if (pSciMapTbl != NULL) {
while (pSciMapTbl->InputPin != 0xFF) {
if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) {
ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin;
if (((pSciMapTbl->InputPin == 0x78 ) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \
((pSciMapTbl->InputPin == 0x79 ) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) {
} else {
LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader);
}
} else {
//Assert Warning "SCI map is invalid"
}
pSciMapTbl++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
*
*
*
* @param[in] pGpioTbl - Table data pointer
* @param[in] FchResetDataBlock
*
*/
VOID
ProgramFchGpioTbl (
IN GPIO_CONTROL *pGpioTbl,
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
)
{
AMD_CONFIG_PARAMS *StdHeader;
UINT32 ddtempVar;
StdHeader = FchResetDataBlock->StdHeader;
if (pGpioTbl != NULL) {
while (pGpioTbl->GpioPin != 0xFF) {
ddtempVar = ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin;
LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->PinFunction, StdHeader);
ddtempVar = ACPI_MMIO_BASE | GPIO_BASE | pGpioTbl->GpioPin;
LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->CfgByte, StdHeader);
pGpioTbl++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
*
*
*
* @param[in] pSataPhyTbl - Table data pointer
* @param[in] FchResetDataBlock
*
*/
VOID
ProgramFchSataPhyTbl (
IN SATA_PHY_CONTROL *pSataPhyTbl,
IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
)
{
AMD_CONFIG_PARAMS *StdHeader;
//UINT32 ddtempVar;
StdHeader = FchResetDataBlock->StdHeader;
if (pSataPhyTbl != NULL) {
while (pSataPhyTbl->PhyData != 0xFFFFFFFF) {
//to be implemented
pSataPhyTbl++;
}
}
}
/**
* GetChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - Hudson-2 chip Strap Status
* @li 0001 - Not USED FWH
* @li 0002 - Not USED LPC ROM
* @li 0004 - EC enabled
* @li 0008 - Reserved
* @li 0010 - Internal Clock mode
* @param[in] StdHeader
*
*/
VOID
GetChipSysMode (
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
}
/**
* IsImcEnabled - Is IMC Enabled
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
*/
BOOLEAN
IsImcEnabled (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 dbSysConfig;
GetChipSysMode (&dbSysConfig, StdHeader);
if (dbSysConfig & ChipSysEcEnable) {
return TRUE;
} else {
return FALSE;
}
}
/**
* GetEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
* @param[in] StdHeader
*
*/
VOID
GetEfuseStatus (
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Or8;
UINT8 Mask8;
Or8 = BIT5;
Mask8 = BIT5;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 ), Value, StdHeader);
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 + 1), Value, StdHeader);
Or8 = 0;
Mask8 = BIT5;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* SbSleepTrapControl - SB Sleep Trap Control
*
*
*
* @param[in] SleepTrap - Whether sleep trap is enabled
*
*/
VOID
SbSleepTrapControl (
IN BOOLEAN SleepTrap
)
{
if (SleepTrap) {
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2;
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) &= ~ (BIT5);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1;
} else {
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) |= BIT5;
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0;
ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
}
}