/* $NoKeywords:$ */ /** * @file * * Various PCI service routines. * * * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ***************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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GnbSmuServiceRequestV4S3Script_ID, ///< SMU service request GnbLibStallS3Script_ID, ///< Stall request PcieLateRestoreTNS3Script_ID, ///< GNB PCIe late restore TN PcieLateRestoreKMS3Script_ID, ///< GNB PCIe late restore KM PcieLateRestoreTHS3Script_ID, ///< GNB PCIe late restore KM GfxRequestSclkTNS3Script_ID ///< SCLk setting } S3_DISPATCH_FUNCTION_ID; #define SAVE_STATE_IO_WRITE_OPCODE 0x00 #define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01 #define SAVE_STATE_MEM_WRITE_OPCODE 0x02 #define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03 #define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04 #define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05 #define SAVE_STATE_STALL_OPCODE 0x07 #define SAVE_STATE_INFORMATION_OPCODE 0x0A #define SAVE_STATE_IO_POLL_OPCODE 0x0D #define SAVE_STATE_MEM_POLL_OPCODE 0x0E #define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F #define SAVE_STATE_DISPATCH_OPCODE 0x20 #define SAVE_STATE_BREAKPOINT_OPCODE 0x21 #define S3_TABLE_LENGTH 8 * 1024 #define S3_TABLE_LENGTH_INCREMENT 1 * 1024 /// S3 Save Table typedef struct { UINT16 TableLength; ///< Table Length UINT32 SaveOffset; ///< Save Location BOOLEAN Locked; ///< Locked } S3_SAVE_TABLE_HEADER; /// S3 write operation header typedef struct { UINT16 OpCode; ///< Opcode ACCESS_WIDTH Width; ///< Data width (byte, word, dword) UINT64 Address; ///< Register address UINT32 Count; ///< Write count } S3_WRITE_OP_HEADER; /// S3 Read and Write Operation header typedef struct { UINT16 OpCode; ///< Opcode ACCESS_WIDTH Width; ///< Data width (byte, word, dword) UINT64 Address; ///< Register Address } S3_READ_WRITE_OP_HEADER; /// S3 Poll operation header typedef struct { UINT16 OpCode; ///< Opcode ACCESS_WIDTH Width; ///< Data width (byte, word, dword) UINT64 Address; ///< Register address UINT64 Delay; ///< Time delay } S3_POLL_OP_HEADER; /// Information operation header typedef struct { UINT16 OpCode; ///< Opcode UINT32 Length; ///< Length of info } S3_INFO_OP_HEADER; /// Dispatch operation header typedef struct { UINT16 OpCode; ///< Opcode UINT16 FunctionId; ///< Function ID UINT16 Length; ///< Length in bytes of the context } S3_DISPATCH_OP_HEADER; typedef VOID S3_DISPATCH_FUNCTION ( IN AMD_CONFIG_PARAMS *StdHeader, IN UINT16 ContextLength, IN VOID *Context ); /// Dispatch function table entry typedef struct { UINT16 FunctionId; ///