/* $NoKeywords:$ */ /** * @file * * AMD Family_15 PCI tables with values as defined in BKDG * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x15 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ****************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Control // F3x6C - Data Buffer Count // bits[30:28] IsocRspDBC = 1 // bits[18:16] UpRspDBC = 1 // bits[7:6] DnRspDBC = 1 // bits[5:4] DnReqDBC = 1 // bits[2:0] UpReqDBC = 2 { PciRegister, { (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision }, {AMD_PF_ALL}, // platformFeatures {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address 0x10010052, // regData 0x700700F7, // regMask }} }, // F3xA0 - Power Control Miscellaneous // bits[13:11] PllLockTime = 1 { PciRegister, { (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision }, {AMD_PF_ALL}, // platformFeatures {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address 0x00000800, // regData 0x00003800, // regMask }} }, // F3xA4 - Reported Temperature Control // bits[12:8] PerStepTimeDn = 0x0F // bits[7] TmpSlewDnEn = 1 // bits[6:5] TmpMaxDiffUp = 3 // bits[4:0] PerStepTimeUp = 0x0F { PciRegister, { (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision }, {AMD_PF_ALL}, // platformFeatures {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address 0x00000FEF, // regData 0x00001FFF, // regMask }} }, // F3x1CC - IBS Control // bits[8] LvtOffsetVal = 1 // bits[3:0] LvtOffset = 0 { PciRegister, { (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision }, {AMD_PF_ALL}, // platformFeatures {{ MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address 0x00000100, // regData 0x0000010F, // regMask }} }, // F4x15C - Core Performance Boost Control // bits[1:0] BoostSrc = 0 { PciRegister, { (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily (AMD_F15_OR_ALL | AMD_F15_TN_ALL | 0x0000000000100000ull) // CpuRevision }, {AMD_PF_ALL}, // platformFeatures {{ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address 0x00000000, // regData 0x00000003, // regMask }} }, }; CONST REGISTER_TABLE ROMDATA F15PciRegisterTable = { PrimaryCores, (sizeof (F15PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), F15PciRegisters, };